Results 101 to 110 of about 6,822 (302)
Nonlinearity-Induced Spur Analysis in Fractional-
IEEE Open Journal of the Solid-State Circuits SocietyA fractional-N frequency synthesizer with low total jitter [e.g., <50fsrms, accounting for both phase noise (PN) and spurs] is essential for enabling the emerging 5G/6G and other high-speed wireless communication standards (e.g., WiFi-6/7).
Yizhe Hu +2 more
doaj +1 more source
High Speed All Digital Phase-Locked Loop
, 2014 摘要 本篇論文描述一個高速全數位鎖相迴路的架構與設計，使用取樣編碼方式，能在四個參考週期內決定DCO操作模式及輸入信號在十六組頻率區段中的位置並局部修改演算流程與DCO設計，使本電路具有較快的搜尋速度、較短的鎖定時間、較小的Phase Jitter，並可操作在極高的頻率。架構中可分為數位控制振盪器，頻率偵測器、相位偵測器、UP/DN Counter、控制單元、啟動電路、取樣電路、編碼電路、位元指標器、除頻器及相位選擇器等十一個部分。操作程序可分為頻率獲取、相位獲取 ...
You, Rung-Hau, 游榮豪
core
Phase-Rotator-Based All-Digital Phase-Locked Loop for a Spread-Spectrum Clock Generator
, 2014 A phase-rotator-based all-digital phase-locked loop for spread-spectrum clock generation is presented. It combines a dual-tone triangular and a random modulation profile to achieve a balance between electromagnetic interference reduction and broadband ...
Lim, Sun-Jae +3 more
core +1 more source
Design and Implementation of Multiple Ring Oscillator-Based TRNG Architecture by Using ADPLL
IEEE AccessA new technique for generating true random numbers by using the ADPLL (All Digital Phase Locked Loop)-based multiple ring oscillator TRNG (MURO-TRNG) is discussed in this paper.
Huirem Bharat Meitei, Manoj Kumar
doaj +1 more source
Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop
, 2018 This All-Digital phase-locked loop uses TSMC90nm process. It uses digital frequency detector and successive approximation register to control the digitally controlled oscillator as well as some control units.
Xie, Shan-yang
core
Advanced Physics Research, EarlyView.Active reactance in electro‐thermal memristors emerges intrinsically from rapid thermal switching of device resistance, linking current‐controlled and voltage‐controlled negative differential resistance to neuronal spiking dynamics. Opposing temperature coefficients of resistance give rise to active inductive or capacitive responses, enabling tunable ...
Fatme Jardali +4 more
wiley +1 more source
Time-to-digital converter for an all-digital phase-locked loop
, 2017 A phase-locked loop (PLL) is a widely-used mixed-signal circuit that is used to create the precise clocks required on almost every integrated circuit. A PLL uses negative feedback to control an on-chip oscillator so that its frequency equals a multiple ...
Sawant, Sanjeet
core
Impedance Spectroscopy of Bifurcation Oscillations in S‐Type Self‐Oscillatory Devices
Advanced Physics Research, EarlyView.Impedance spectroscopy (IS) reveals stability regimes and bifurcation dynamics in S‐type self‐oscillatory devices. By linking nonlinear control theory with frequency‐domain measurements, experimental signatures of oscillations, entrainment, and phase locking are directly identified.
Gonzalo Rivera‐Sierra +5 more
wiley +1 more source
All-digital Clock and Data Recovery and All-digital Phase-locked Loop
, 2010 近幾年來，在製程的定位上都是以減少電晶體尺寸為主，這可使電路設計上得到更高的操作頻率和更少的功率消耗，卻不利於類比電路設計，反之，更適合數位電路設計，因此已有許多的類比電路改以數位方式實現，例如，鎖相迴路和資料時脈回復電路。 在論文中，1.25Gbps全數位資料時脈回復電路被提出，由於累加器時脈頻率的限制，因此提出由預先累加器和具有定標器的路徑(第一積分路徑)來降低累加器的時脈頻率及迴路延遲，藉由降低迴路延遲可使用較小的正比路徑增益來獲得較低的時脈抖動，卻不會犧牲相位邊限 ...
陳易楓, Chen, I-Fong
core
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
, 2011 A divider-less all digital phase locked loop (ADPLL) with a high frequency resolution is implemented. All blocks excluding digitally controlled oscillator (DCO) and time to digital converter (TDC) are realized in standard digital design which consumes ...
Abdulaziz, Mohammed +8 more
core +1 more source