Results 41 to 50 of about 84,601 (236)
Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques
IEEE Open Journal of the Solid-State Circuits SocietyThis article proposes an mm-wave fractional-N all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, consequently improving jitter at lower power ...
Teerachot Siriburanon +3 more
doaj +1 more source
All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops
IET Circuits, Devices and Systems, 2021 Charge‐pump phase‐locked loop (CP‐PLL) is widely used to generate timing signals in systems on chips (SoCs). However, the number of cores embedded in SoCs, the limited I/O port resources and the cost of external test equipment lead to the increase of ...
Lanhua Xia, Jifei Tang
doaj +1 more source
HKROC: An integrated front-end ASIC to read out photomultiplier tubes for large neutrino experiments [PDF]
EPJ Web of ConferencesThe HKROC ASIC was originally designed to read out the photomultiplier tubes (PMTs) for the Hyper-Kamiokande (HK) experiment. HKROC is a very innovative ASIC capable to read out a large number of channels satisfying stringent requirements in terms of ...
Dulucq Frederic +17 more
doaj +1 more source
Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops [PDF]
, 2009 This brief analyzes the jitter as well as the power dissipation of phase-locked loops (PLLs). It aims at defining a benchmark figure-of-merit (FOM) that is compatible with the well-known FOM for oscillators but now extended to an entire PLL.
Gao, X. +3 more
core +2 more sources
Design and Emulation of All-Digital Phase-Locked Loop on FPGA
Electronics, 2019 This paper demonstrates the design and implementation of an all-digital phase-lockedloop (ADPLL) on Field Programmable Gate Array (FPGA). It is useful as an emulation techniqueto show the feasibility and effectiveness of the ADPLL in the early design ...
Saichandrateja Radhapuram +2 more
semanticscholar +1 more source
A Background Jitter Calibration for ADCs Using TDC Phase Information From ADPLL
IEEE AccessThe phase noise, commonly known as jitter, in Phase-Locked Loops (PLLs) is conventionally perceived as a stochastic process, necessitating a degree of tolerance in downstream circuits such as Analog-to-Digital Converters (ADCs). This paper addresses this
Haoyang Shen +4 more
doaj +1 more source
Theoretical Modeling and Simulation of Phase-Locked Loop (PLL) for Clock Data Recovery (CDR)
International Islamic University Malaysia Engineering Journal, 2012 Modern communication and computer systems require rapid (Gbps), efficient and large bandwidth data transfers. Agressive scaling of digital integrated systems allow buses and communication controller circuits to be integrated with the microprocessor on ...
Zainab Mohamad Ashari +1 more
doaj +1 more source
Multi-color Cavity Metrology [PDF]
, 2012 Long baseline laser interferometers used for gravitational wave detection have proven to be very complicated to control. In order to have sufficient sensitivity to astrophysical gravitational waves, a set of multiple coupled optical cavities comprising ...
Adhikari, Rana X. +13 more
core +2 more sources
Information and Telecommunication Sciences, 2018 Background. The generating reference time signals problem to meet the all consumers’ requirements for time and frequency information is targeted on researching the time scale IP-technologies transmission systems quality improvement and optimizing the ...
Dmytro Kalian
doaj +1 more source
Nanosecond channel-switching exact optical frequency synthesizer using an optical injection phase-locked loop (OIPLL) [PDF]
, 2004 Experimental results are reported on an optical frequency synthesizer for use in dynamic dense wavelength-division-multiplexing networks, based on a tuneable laser in an optical injection phase-locked loop for rapid wavelength locking.
Bayvel, P +6 more
core +1 more source