Results 61 to 70 of about 6,822 (302)

Time-Domain ADPLL BPSK, QPSK, and 8PSK Demodulators

open access: yesJournal of Electrical and Computer Engineering
Time-domain all-digital-phase-locked-loop phase-shift-keying (PSK) demodulators are proposed for BPSK, QPSK, and 8PSK signals. The demodulator architectures are highly suitable for low-voltage nanoscale CMOS techology.
Phanumas Khumsat   +3 more
doaj   +1 more source

Phase Locked-Loop Design of High-Order Automotive Frequency Modulated Continuous Wave Radar Based on Fast Integration Structure

open access: yesIEEE Access
In recent years, frequency-modulated continuous-wave (FMCW) radars have been widely used in the automotive field to measure the relative distance and speed of external targets.
Mengwei Yang   +2 more
doaj   +1 more source

Toward Long‐Term Reliable Human‐Machine Interaction: A Flexible, Breathable, and Self‐Powered Pressure Sensor System With Firefighting Validation

open access: yesAdvanced Science, EarlyView.
This work develops a breathable potentiometric self‐powered pressure sensor with good wearability, using a non‐woven fabric substrate and hydrogel electrolyte. The sensor is integrated into a five‐channel smart glove to acquire reliable hand motion signals, which are processed by a CNN for identity verification and smart vehicle control in human ...
Qilong Zhang   +10 more
wiley   +1 more source

All-digital phase-locked loop in 40 nm CMOS for 5.8 Gbps serial link transmitter

open access: yes, 2015
This paper describes an all-digital phase-locked loop based clock generator for a MIPI M-PHY serial link transmitter. The paper focuses on ADPLL phase accumulator speed optimization, PVT calibration, loop type changing criteria and power saving in phase ...
Tikka, Tero   +7 more
core   +1 more source

A Second Harmonic Current Suppression Strategy Based on a Digital Band-Stop Filter With Center Frequency Tracking Grid Frequency

open access: yesIEEE Access
In a single-phase grid-tie system, the presence of a second harmonic current (SHC) on the DC side reduces the conversion efficiency and lifetime of the DC source.
Jun-Hyeong Kwon   +4 more
doaj   +1 more source

Wavelength‐Dependent Photobiomodulation Regulates Macrophage Polarization via Mitochondrial Dynamics and Metabolic Reprogramming

open access: yesAdvanced Science, EarlyView.
Light wavelength encodes distinct macrophage fates through mitochondrial and metabolic remodeling. Red 625 nm irradiation induces glycolysis, mitochondrial fission, and M1 polarization, whereas near‐infrared 850 nm irradiation promotes fatty acid oxidation, mitochondrial fusion, and M2 polarization.
Qiusheng Shi   +12 more
wiley   +1 more source

The Implementation and Analysis of an All-digital Phase-locked Loop

open access: yes, 2012
[[abstract]]An all-digital phase-locked loop (ADPLL) circuit is presented. The feature of the ADPLL is that its resolution in the phase detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time.
Chen, Po-Yueh; Su, Hung-Lung
core  

An Interpolated Flying-Adder-Based Frequency Synthesizer

open access: yesJournal of Electrical and Computer Engineering, 2011
This work presents an interpolated flying-adder- (FA-) based frequency synthesizer. The architecture of an interpolated FA, which uses an interpolated multiplexer (MUX) to replace the multiplexer in conventional flying adder, improves the cycle-to-cycle ...
Pao-Lung Chen, Chun-Chien Tsai
doaj   +1 more source

Boosting Ferroelectricity: 2D and Polymer Ferroelectric Hybrids Enabling Ambipolar Nonvolatile MoS2 Memory Transistor

open access: yesAdvanced Science, EarlyView.
Two‐dimensional CuInP2S6 nanosheets are incorporated into a P(VDF‐TrFE) matrix to induce polarization‐cooperative ferroelectric coupling. The resulting P(VDF‐TrFE)/CuInP2S6 hybrid film exhibits reinforced ferroelectric ordering and reduced coercive electric fields compared with pristine P(VDF‐TrFE).
Yeonsu Jeong   +10 more
wiley   +1 more source

Design and analysis of high performance low noise oscillators and phase lock loops

open access: yes, 2010
The design and implementation of high purity, high speed and power efficient clock generation Integrated Circuits continue to be one the greatest challenges facing IC designers today. In order to address this challenge, this thesis considers the modeling
Ke, Li
core  

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