Results 51 to 60 of about 84,601 (236)
Signal Synchronization, Collection and Transmission for Multichannel Distribution Seismic Antenna
Известия высших учебных заведений России: Радиоэлектроника, 2018 Creation of seismic antennas involves production of a system capable to provide synchronous analog-to- digital data signal conversion of all channels and to broadcast digitized signals to the central computing complex (CCC).
A. D. Volodin +3 more
doaj +1 more source
Design and Implementation of FPGA based linear All Digital Phase-Locked Loop for Signal Processing Applications [PDF]
, 2012 This project presents a linear all-digital phase locked loop based on FPGA. In this ADPLL the phase detection system is realized by generating an analytic signal using a compact implementation of Hilbert transform and then simply computing the ...
Das, Abhishek, Dash, Suraj
core
A Scalable, Self-Analyzing Digital Locking System for use on Quantum Optics Experiments
, 2011 Digital control of optics experiments has many advantages over analog control systems, specifically in terms of scalability, cost, flexibility, and the integration of system information into one location.
B. C. Buchler +6 more
core +1 more source
Noise shaping Asynchronous SAR ADC based time to digital converter [PDF]
, 2018 Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits.
Katragadda, Sowmya
core +1 more source
DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW
Jurnal Teknologi, 2019 Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS)
Florence Choong +6 more
semanticscholar +1 more source
Analysis and equalization of data-dependent jitter [PDF]
, 2006 Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems and aggravates synchronization in phase- and delay-locked loops used for data recovery.
Buckwalter, James F., Hajimiri, Ali
core +1 more source
Phase Locked Loop Test Methodology [PDF]
, 2008 Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based.
Burbidge, Martin, Richardson, Andrew
core
Mokslas: Lietuvos Ateitis, 2016 Frequency synthesiser is one of most important blocks in wire-less transceiver. Generally phase locked loop (PLL) is used as frequency synthesiser in multistandart wireless transceivers.
Marijan Jurgo, Romualdas Navickas
doaj +1 more source
Digital second-order phase-locked loop [PDF]
, 1973 A digital second-order phase-locked loop is disclosed in which a counter driven by a stable clock pulse source is used to generate a reference waveform of the same frequency as an incoming waveform, and to sample the incoming waveform at zero-crossover ...
Carl, C., Holes, J. K., Tegnelia, C. R.
core +1 more source
Versatile Digital GHz Phase Lock for External Cavity Diode Lasers
, 2009 We present a versatile, inexpensive and simple optical phase lock for applications in atomic physics experiments. Thanks to all-digital phase detection and implementation of beat frequency pre-scaling, the apparatus requires no microwave-range reference ...
Appel, Jürgen +2 more
core +1 more source