Results 41 to 50 of about 2,863,776 (144)

Demonstration of a Graphene Adjustable‐Barriers Phototransistor with Tunable Ultra‐High Responsivity

Advanced Optical Materials, Volume 13, Issue 18, June 26, 2025.
A novel graphene‐based phototransistor with a tunable ultra‐high responsivity of 1.7 x 107 AW−1 has been demonstrated. Due to the selected material combination of amorphous silicon, graphene and n‐germanium, the device is potentially capable of dual‐band detection in the VIS‐IR range.
Carsten Strobel, Carlos A. Chavarin, Martin Knaut, Christian Wenger, André Heinzig, Thomas Mikolajick   +5 more
wiley   +1 more source

A novel current‐source management integrated circuit applied to high‐voltage integrated gate commutated thyristor gate driver

High Voltage, Volume 10, Issue 3, Page 533-545, June 2025.
Abstract This paper presents a fully customised integrated gate commutated thyristor (IGCT) gate driver monolithic integrated circuit (GDMIC), aiming to address the many shortcomings of traditional IGCT gate driver units composed of discrete components, such as the excessive number of components, low reliability, and complex development processes.
Shiping Chen, Zhanqing Yu, Jiaxu Shi, Zhengyu Chen, Lu Qu, Jinpeng Wu, Rong Zeng   +6 more
wiley   +1 more source

Area‐efficient ultra‐wide‐tuning‐range ring oscillators in 65‐nm complementary metal–oxide–semiconductor

International Journal of Circuit Theory and Applications, Volume 53, Issue 3, Page 1253-1291, March 2025.
FIGURE 1. Comparison between the proposed method and prior state‐of‐the‐art: (a) TR vs. frequency; (b) FOMT vs. frequency. FIGURE 2. Comparison between the proposed method and prior art: (a) FOMTA vs. frequency; (b) TR vs. area. These designs showcase the versatility and efficiency of the two‐mode current‐starved delay architecture, which offers wide ...
Chaowei Yang, Yong Chen, Kai Cheng, Crovetti Paolo Stefano, Rui P. Martins, Pui‐In Mak   +5 more
wiley   +1 more source

Energy-Efficient Aggressive Duty-Cycling of V-Band Power Amplifiers

IEEE Access
In addition to implementing the core functionality, a design goal for modern circuits is reduced energy consumption. When options for improving active state efficiency are eventually exhausted, the next step is to aggressively minimize the duration a ...
Maximilian Gottfried Becker, Marco Gunia, Diego Mendez, Frank Ellinger   +3 more
doaj   +1 more source

A Cascode Pair Based on SiGe HPT for RoF/LiFi Applications

Electronics Letters, Volume 61, Issue 1, January/December 2025.
In this letter, a Si/SiGe phototransistor fully integrated in an industrial 55‐nm node BiCMOS technology is incorporated in a cascode pair for high‐speed photodetection. After having presented the phototranistor structure, the opto‐microwave performances are discussed and compared with a single stage phototransistor.
Thary Valentin, Algani Catherine, Chevalier Pascal, Polleux Jean‐Luc   +3 more
wiley   +1 more source

A highly flexible ROM generator for BiCMOS technology

, 2022
S.33-36This paper describes a highly flexible design rule independent ROM generator for BiCMOS technology with full CAD support for compilation, verification, simulation, and documentation.
Eßer, W., Weghaus, B., Schardein, W., Wittmann, R.   +3 more
core   +1 more source

A Programmable Gain Amplifier With Temperature Compensation for Hall Sensor

Electronics Letters, Volume 61, Issue 1, January/December 2025.
This work presents a high‐performance programmable gain amplifier (PGA) incorporating advanced temperature compensation technology. The proposed compensation scheme achieves remarkable thermal stability, maintaining sensitivity drift below 0.3% across an extended temperature range from −40°C to 140°C.
Kaixin Fan, Long Li, Haozhe Zhang, Hongmei Chen, Dong Huang, Yongsheng Yin   +5 more
wiley   +1 more source

A 18‐36 GHz Noise Cancelling Low‐Noise Amplifier With 2.9 dB NF in 130 nm SiGe BiCMOS

Electronics Letters, Volume 61, Issue 1, January/December 2025.
This paper presents a broadband noise‐canceling low‐noise amplifier (LNA) implemented in a 130‐nm SiGe BiCMOS process. The first stage employs a parallel architecture, combining a common‐base amplifier with a resistive feedback common‐emitter amplifier, to achieve noise cancellation.
Wenyan lyu, Peigen Zhou, Jixin Chen, Dawei Tang, Zekun Li, Wei Hong   +5 more
wiley   +1 more source

A charge-trapping-based technique to design low-voltage BiCMOS logic circuits

, 1998
New BiCMOS logic circuits employing a charge trapping technique are presented. The circuits include an XOR gate and an adder. Submicrometer technologies are used in the simulation and the circuits’ performances are comparatively evaluated ...
Yeo, Kiat Seng, Rofail, Samir S.
core   +1 more source

Millimeter-Wave Phased Arrays in Silicon [PDF]

, 2007
Integration of mm-wave multiple-antenna systems on silicon-based processes enables complex, low-cost systems for high-frequency communication and sensing applications.
Natarajan, Arun Sridhar
core   +1 more source