Structurally optimized SiC CMOS FinFET for high-temperature and low-power SoC logic integration. [PDF]
Kwon TS +7 more
europepmc +1 more source
3-Levels Vertically Stacked Si Nanosheet GAA pFETs with Low-Temperature Interface Treatment for Cryogenic Application. [PDF]
Qian L +6 more
europepmc +1 more source
High-Performance P- and N-Type SiGe/Si Strained Super-Lattice FinFET and CMOS Inverter: Comparison of Si and SiGe FinFET. [PDF]
Yao YJ +8 more
europepmc +1 more source
From Field Effect Transistors to Spin Qubits: Focus on Group IV Materials, Architectures and Fabrications. [PDF]
Petkov N, Fagas G.
europepmc +1 more source
Design of low power and high speed approximate multipliers utilizing current mode 4 to 2 compressors based on CNTFET technology. [PDF]
Foroutan P, Navi K.
europepmc +1 more source
Development and Performance Analysis of High-K Spacer-Induced Strained Si/SiGe Channel-Based Gate All Around FET for Thermal Effects. [PDF]
Yugender P +6 more
europepmc +1 more source
Cross-architecture tuning of silicon and SiGe-based quantum devices using machine learning. [PDF]
Severin B +21 more
europepmc +2 more sources
High-voltage FinFET with floating poly and high-k material for enhanced intrinsic gain and safe operating area. [PDF]
Oh K +8 more
europepmc +1 more source
Dual-directional CIM-based non-volatile SRAM for instant-on/off energy-constrained edge AI devices. [PDF]
Hemmasi SP +3 more
europepmc +1 more source

