Results 41 to 50 of about 18,840,038 (173)

Low‐temperature SOI SiGe/Si superlattice FinFET with omega‐shaped channel and self‐allied silicide for 3D sequential IC

Electronics Letters
In this letter, to improve the performance and reduce leakage currents of bulk low‐temperature multi‐layer SiGe/Si superlattice (SL) fin field‐effect transistors (FinFETs), a p‐type omega‐shaped channel (Ω‐channel) SL FinFET is realized by etching a Si ...
Xu‐Lei Qin, Guan‐Qiao Sang, Lei Cao, Qing‐Kun Li, Ren‐Jie Jiang, Yan‐Zhao Wei, Jun‐Feng Li, Jia‐Xin Yao, Mei‐He Zhang, Qing‐Zhu Zhang, Hua‐Xiang Yin   +10 more
doaj   +1 more source

Understanding Frequency Dependence of Trap Generation Under AC Positive Bias Temperature Instability Stress in Si n-FinFETs

IEEE Journal of the Electron Devices Society
In this paper, the frequency (f) dependence of trap generation in Si n-channel fin field-effect transistors (n-FinFETs) under AC positive bias temperature instability (PBTI) stress is investigated by fast direct-current current-voltage (DCIV) method and ...
Yunfei Shi, Hao Chang, Hong Yang, Qiangzhu Zhang, Qianqian Liu, Bo Tang, Longda Zhou, Zhigang Ji, Junjie Li, Xiaobin He, Junfeng Li, Huaxiang Yin, Xiaolei Wang, Jun Luo, Wenwu Wang   +14 more
doaj   +1 more source

Computational design of two‐dimensional MA2Z4 family field‐effect transistor for future Ångström‐scale CMOS technology nodes

InfoMat, EarlyView.
Two‐dimensional MA2Z4 such as MoSi2N4 offer a new path to extend transistor scaling beyond the limits of silicon. Due to their exceptional properties, these 2D semiconductors are promising candidates for future Ångström‐scale CMOS technology. This review outlines the computational design and roadmap bridging materials discovery, device design and ...
Che Chen Tho, Zongmeng Yang, Shibo Fang, Shiying Guo, Liemao Cao, Chit Siong Lau, Fei Liu, Shengli Zhang, Jing Lu, L. K. Ang, Lain‐Jong Li, Yee Sin Ang   +11 more
wiley   +1 more source

Leakage Power Reduction for Deeply-Scaled FinFET Circuits Operating in Multiple Voltage Regimes Using Fine-Grained Gate- Length Biasing Technique [PDF]

, 2020
-With the aggressive downscaling of the process technologies and importance of battery-powered systems, reducing leakage power consumption has become one of the most crucial design challenges for IC designers.
Ji Li, Massoud Pedram, Qing Xie, Shahin Nazarian, Yanzhi Wang   +4 more
core  

Carrier Mapping in Sub‐2nm Node Nanosheet Transistors with Scanning Spreading Resistance Microscopy

Small Methods, EarlyView.
Within this work, advancements in scanning spreading resistance microscopy (SSRM) allow charge carrier mapping within 5.5 nm‐thick nanosheet channels. Devices subjected to rapid thermal annealing at 950°C show ∼ 5 nm enhanced phosphorus diffusion, with profiles in close agreement with semi‐atomistic process simulations.
Andrea Pondini, Pierre Eyben, Lennaert Wouters, Albert Minj, Thomas Hantschel, Philippe Matagne, Jérôme Mitard, Anne Verhulst   +7 more
wiley   +1 more source

Unified Analytic Framework for Thickness‐Dependent Transport and Trap‐State Modulation in Ultrathin W:In2O3 Field‐Effect Transistors

Small Structures, Volume 7, Issue 2, February 2026.
We present a unified analytic framework linking subthreshold and above‐threshold conduction in oxide field‐effect transistors by decomposing the drain current into band transport, tail‐state percolation, and interface‐trap diffusion components. Parameter correlation and identifiability analyses enable robust extraction of physical metrics, yielding ...
Mochamad Januar, Zhao‐Feng Luo, Kou‐Chen Liu, Min‐Hung Lee   +3 more
wiley   +1 more source

Impacts of Local Oxide Trapped Charge on Electrical and Capacitance Characteristics of SOI FinFet

East European Journal of Physics
In this work, the influence of the local oxide trapped charge on the transfer Id-Vg characteristics and capacitance of the gatetoI. INTRODUCTION source (drain) connection of the silicon-on-insulator (SOI) structure-based FinFET is simulated.
Atabek Atamuratov, Ibroximjon Karimov, Mirzabahrom Foziljonov, Azamat Abdikarimov, Odilbek Atamuratov, Makhkam Khalilloev   +5 more
doaj   +1 more source

Ultra‐Fast, Low‐Resistance Nano Gap Electromechanical Switch for Power Gating Applications

Advanced Electronic Materials, Volume 12, Issue 2, 21 January 2026.
An ultra‐small 20 nm air gap and a high‐stiffness architecture enable a MEMS power‐gating switch that combines 0.95 Ω on‐resistance with 30 ns switching while maintaining off‐state leakage below 100 fA. Fabricated below 200 °C, the device is compatible with BEOL and monolithic 3D integration, overcoming the long‐standing resistance–speed trade‐off ...
Tae‐Soo Kim, So‐Young Lee, Yu‐Hyun Shim, Sung‐Ho Kim, Yong‐Bok Lee, Jun‐Bo Yoon   +5 more
wiley   +1 more source

Utilizing MRAMs With Low Resistance and Limited Dynamic Range for Efficient MAC Accelerator

IEEE Open Journal of Nanotechnology
The recent advancements in data mining, machine learning algorithms and cognitive systems have necessitated the development of neuromorphic processing engines which may enable resource and computationally intensive applications on the internet-of-Things (
Sateesh, Kaustubh Chakarwar, Shubham Sahay   +2 more
doaj   +1 more source

Kolmogorov–Arnold Network for Transistor Compact Modeling

Advanced Intelligent Systems, Volume 8, Issue 1, January 2026.
This work introduces Kolmogorov–Arnold network (KAN) for the transistor—an architecture that integrates interpretability with high precision in physics‐based function modeling. The results reveal that despite achieving superior prediction accuracy for critical figures of merit, KAN demonstrates unique inherent challenges for transistor modeling ...
Rodion Novkin, Hussam Amrouch
wiley   +1 more source