Results 11 to 20 of about 134,754 (281)
Don't make cache too complex: A simple probability-based cache management scheme for SSDs. [PDF]
PLoS ONE, 2017 Solid-state drives (SSDs) have recently become a common storage component in computer systems, and they are fueled by continued bit cost reductions achieved with smaller feature sizes and multiple-level cell technologies.
Seungjae Baek +2 more
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Decision Tree-Based Adaptive Reconfigurable Cache Scheme
Algorithms, 2021 Applications have different preferences for caches, sometimes even within the different running phases. Caches with fixed parameters may compromise the performance of a system.
Wei Zhu, Xiaoyang Zeng
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IOb-Cache: A High-Performance Configurable Open-Source Cache
Algorithms, 2021 Open-source processors are increasingly being adopted by the industry, which requires all sorts of open-source implementations of peripherals and other system-on-chip modules.
João V. Roque +3 more
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DyCache: Dynamic Multi-Grain Cache Management for Irregular Memory Accesses on GPU
IEEE Access, 2018 GPU utilizes the wide cache-line (128B) on-chip cache to provide high bandwidth and efficient memory accesses for applications with regularly-organized data structures.
Hui Guo +4 more
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Cache miss analysis of WHT algorithms [PDF]
Discrete Mathematics & Theoretical Computer Science, 2005 On modern computers memory access patterns and cache utilization are as important, if not more important, than operation count in obtaining high-performance implementations of algorithms.
Mihai Furis +2 more
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, 2005 Cache memories are commonly implemented through multiple memory banks to improve bandwidth and latency. The early knowledge of the data cache bank that an instruction will access can help to improve the performance in several ways.
Bieschewski, Stefan +2 more
core +1 more source
IEEE Access, 2021 Monolithic 3D (M3D) integration has been emerged as a promising technology for fine-grained 3D stacking. As the M3D integration offers extremely small dimension of via in a nanometer-scale, it is beneficial for small microarchitectural blocks such as ...
Young-Ho Gong
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Randomized cache placement for eliminating conflicts [PDF]
, 1999 Applications with regular patterns of memory access can experience high levels of cache conflict misses. In shared-memory multiprocessors conflict misses can be increased significantly by the data transpositions required for parallelization.
González Colás, Antonio María +1 more
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Accelerator Memory Reuse in the Dark Silicon Era [PDF]
, 2014 Accelerators integrated on-die with General-Purpose CPUs (GP-CPUs) can yield significant performance and power improvements. Their extensive use, however, is ultimately limited by their area overhead; due to their high degree of specialization, the ...
Carloni, L.P. +4 more
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MESI Cache Coherence Simulator for Teaching Purposes
CLEI Electronic Journal, 2009 Nowadays, the computational systems (multi and uniprocessors) need to avoid the cache coherence problem. There are some techniques to solve this problem. The MESI cache coherence protocol is one of them.
Juan Gómez-Luna +2 more
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