Results 51 to 60 of about 108 (78)

Adaptive Model Predictive Controller to Reduce Switching Losses for a Capacitor-Less D-STATCOM

IEEE Open Journal of Power Electronics, 2020
In the post-industrial digital-economy, motors powering manufacturing have been replaced by computers powering ecommerce - with significant financial losses attributable to poor power quality (PQ).
Wesam Rohouma, Morcos Metry, Robert S. Balog, Aaqib Ahmad Peerzada, Miroslav M. Begovic   +4 more
doaj   +1 more source

The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET

Nanoscale Research Letters, 2017
The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM).
Wei Li, Hongxia Liu, Shulong Wang, Shupeng Chen, Qianqiong Wang   +4 more
doaj   +1 more source

Capacitorless One-Transistor Dynamic Random-Access Memory with Novel Mechanism: Self-Refreshing

Nanomaterials
In this paper, we propose for the first time a self-refreshing mechanism in a junctionless field-effect transistor (JLFET) based on one-transistor dynamic random-access memory (1T-DRAM) with a silicon-on-insulator (SOI) structure.
Sang Ho Lee, Jin Park, Young Jun Yoon, In Man Kang   +3 more
doaj   +1 more source

A capacitor-less low drop-out voltage regulator with hybrid lead-miller compensation

Scientific Reports
This paper presents a new external capacitor-less voltage regulator (LDO) using a hybrid lead-Miller compensation to create stability and reduce the total on-chip capacitor.
Mostafa Piri, Emad Ebrahimi, Mohammad Ahmadi   +2 more
doaj   +1 more source

A Low-Energy High-Density Capacitor-Less I&F Neuron Circuit Using Feedback FET Co-Integrated With CMOS

IEEE Journal of the Electron Devices Society, 2019
We have developed a capacitor-less I&F neuron circuit with a dual gate positive feedback fieldeffect transistor (FBFET) and successfully co-integrated FBFET and CMOS in a wafer.
Min-Woo Kwon, Kyungchul Park, Myung-Hyun Baek, Junil Lee, Byung-Gook Park   +4 more
doaj   +1 more source

An Output Capacitor-Less Low-Dropout Regulator with 0–100 mA Wide Load Current Range

Energies, 2019
An output capacitor-less low-dropout (OCL-LDO) regulator with a wide range of load currents is proposed in this study. The structure of the proposed regulator is based on the flipped-voltage-follower LDO regulator.
Jihoon Park, Woong-Joon Ko, Dong-Seok Kang, Yoonmyung Lee, Jung-Hoon Chun   +4 more
doaj   +1 more source

A Fast Transient Response Capacitor-Less LDO with Transient Enhancement Technology

Micromachines
This paper proposes a fast transient load response capacitor-less low-dropout regulator (CL-LDO) for digital analog hybrid circuits in the 180 nm process, capable of converting input voltages from 1.2 V to 1.8 V into an output voltage of 1 V.
Chufan Chen, Mengyuan Sun, Leiyi Wang, Teng Huang, Min Xu   +4 more
doaj   +1 more source

High performance Si-MoS2 heterogeneous embedded DRAM

Nature Communications
Embedded Dynamic RAM (eDRAM) has become a key solution for large-capacity cache in high-performance processors. A heterogeneous two transistor capacitorless eDRAM (2T-eDRAM) that combines silicon and molybdenum disulfide (MoS2) is reported to address the
Kai Xiao, Jing Wan, Hui Xie, Yuxuan Zhu, Tian Tian, Wei Zhang, Yingxin Chen, Jinshu Zhang, Lihui Zhou, Sheng Dai, Zihan Xu, Wenzhong Bao, Peng Zhou   +12 more
doaj   +1 more source

A Review on Frequency Compensation and Transient Enhancement Schemes of Flipped Voltage Follower LDO Regulators for SoC Applications

IEEE Access
The low dropout (LDO) regulator is an essential circuit in the wireless power module of any portable device. The power management integrated circuits demand low power, high performance LDO regulator.
P. Manikandan, B. Bindu
doaj   +1 more source

Schottky barrier memory based on heterojunction bandgap engineering for high-density and low-power retention

Discover Nano
Dynamic random-access memory (DRAM) has been scaled down to meet high-density, high-speed, and low-power memory requirements. However, conventional DRAM has limitations in achieving memory reliability, especially sufficient capacitance to distinguish ...
Hyangwoo Kim, Yijoon Kim, Kyounghwan Oh, Ju Hong Park, Chang-Ki Baek   +4 more
doaj   +1 more source