Results 41 to 50 of about 51,131 (290)
Imaging Fermi-level hysteresis in nanoscale bubbles of few-layer MoS2
The electrical stability and reliability of two-dimensional (2D) crystal-based devices are mainly determined by charge traps in the device defects. Although nanobubble structures as defect sources in 2D materials strongly affect the device performance ...
Dohyeon Jeon +3 more
doaj +1 more source
Nitrided SrTiO 3 as charge-trapping layer for nonvolatile memory applications [PDF]
Charge-trapping characteristics of SrTiO 3 with and without nitrogen incorporation were investigated based on Al/ Al 2 O 3/SrTiO 3/SiO 2 /Si (MONOS) capacitors.
Huang, XD, Lai, PT, Liu, L, Xu, JP
core +1 more source
Van der Waals engineering of ferroelectric heterostructures for long-retention memory
The memory retention for a ferroelectric field-effect transistor is limited by the depolarization effects and carrier charge trapping. Here, the authors fabricate a long-retention memory cell with a metal-ferroelectric-metal-insulator-semiconductor ...
Xiaowei Wang +12 more
doaj +1 more source
Enhanced memory effect with embedded graphene nanoplatelets in znO charge trapping layer [PDF]
Cataloged from PDF version of article.A charge trapping memory with graphene nanoplatelets embedded in atomic layer deposited ZnO (GNIZ) is demonstrated.
Alkis, S. +4 more
core +1 more source
Write‐once‐read‐many (WORM) memory behavior is often observed in polymer electret memory (PEM) devices, greatly limiting their overall performance. This paper systematically investigates the device physics of PEM devices with poly(α‐methylstyrene) as a ...
Waner He +12 more
doaj +1 more source
This study aimed to propose a silicon-on-insulator (SOI)-based charge-trapping synaptic transistor with engineered tunnel barriers using high-k dielectrics for artificial synapse electronics capable of operating at high temperatures.
Dong-Hee Lee, Hamin Park, Won-Ju Cho
doaj +1 more source
Monolayer optical memory cells based on artificial trap-mediated charge storage and release
Memory devices are key building blocks of image sensing circuitry. Here, the authors demonstrate a MoS2monolayer optoelectronic memory device based on charge trapping and subsequent optically-induced charge release, capable of 12-bit operation.
Juwon Lee +10 more
doaj +1 more source
Negative Differential Resistance, Memory and Reconfigurable Logic Functions based on Monolayer Devices derived from Gold Nanoparticles Functionalized with Electro-polymerizable Thiophene-EDOT Units [PDF]
We report on hybrid memristive devices made of a network of gold nanoparticles (10 nm diameter) functionalized by tailored 3,4(ethylenedioxy)thiophene (TEDOT) molecules, deposited between two planar electrodes with nanometer and micrometer gaps (100 nm ...
Alibart, F. +9 more
core +4 more sources
This study investigates the tribological response of 60NiTi alloy under dry, water‐lubricated and high‐temperature conditions. The alloy exhibits decreasing wear volume and friction with increasing temperature due to the formation of protective oxide layers. The work clarifies dominant wear mechanisms and demonstrates the suitability of 60NiTi for high‐
Anthony Onyebuchi Okoani +2 more
wiley +1 more source
Ga2O3(Gd2O3) as Charge-Trapping Layer for Nonvolatile Memory Applications [PDF]
published_or_final_versio
Huang, X, Lai, PT, Sin, JKO
core +2 more sources

