Results 121 to 130 of about 441 (179)

Network-on-Chip virtualization in Chip-Multiprocessor Systems

Journal of Systems Architecture, 2012
[EN] It is expected that Chip Multiprocessor Systems (CMPs) will contain more and more cores in every new generation. However, applications for these systems do not scale at the same pace. In order to obtain a good CMP utilization several applications will need to coexist in the system and in those cases virtualization of the CMP system will become ...
JOSÉ L Sanchez, JOSÉ Flich, FRANCISCO J Alfaro   +2 more
exaly   +5 more sources

Heterogeneous chip multiprocessors

Computer, 2005
Heterogeneous (or asymmetric) chip multiprocessors present unique opportunities for improving system throughput, reducing processor power, and mitigating Amdahl's law. On-chip heterogeneity allow the processor to better match execution resources to each application's needs and to address a much wider spectrum of system loads - from low to high thread ...
Rakesh Kumar 0002, Dean M. Tullsen, Norman P. Jouppi, Parthasarathy Ranganathan   +3 more
openaire   +1 more source

A single-chip multiprocessor

Computer, 1997
Presents the case for billion-transistor processor architectures that will consist of chip multiprocessors (CMPs): multiple (four to 16) simple, fast processors on one chip. In their proposal, each processor is tightly coupled to a small, fast, level-one cache, and all processors share a larger level-two cache.
Lance Hammond, Basem A. Nayfeh, Kunle Olukotun   +2 more
openaire   +1 more source

Future of multiprocessors: Heterogeneous Chip Multiprocessors

2012 International Conference on Informatics, Electronics & Vision (ICIEV), 2012
As computer applications are becoming complex, large and versatile; the advent of Chip multiprocessor is ubiquitous. There are numerous researches going on about the core architectures within the chip. Heterogeneous Chip Multiprocessor (CMP) is leading the innovation. Heterogeneous CMP is composed of cores of varying performance, and complexity.
null Mohammad Abdul Qayum, null Nafiul Alam Siddique, null Mohammad Atiqul Haque, Abu Saleh Md. Tayeen   +3 more
openaire   +1 more source

Parallel buffers for chip multiprocessors

Proceedings of the 3rd international workshop on Data management on new hardware, 2007
Chip multiprocessors (CMPs) present new opportunities for improving database performance on large queries. Because CMPs often share execution, cache, or bandwidth resources among many hardware threads, implementing parallel database operators that efficiently share these resources is key to maximizing performance.
John Cieslewicz, Kenneth A. Ross, Ioannis Giannakakis   +2 more
openaire   +1 more source

Data partitioning on chip multiprocessors

Proceedings of the 4th international workshop on Data management on new hardware, 2008
Partitioning is a key database task. In this paper we explore partitioning performance on a chip multiprocessor (CMP) that provides a relatively high degree of on-chip thread-level parallelism. It is therefore important to implement the partitioning algorithm to take advantage of the CMP's parallel execution resources.
John Cieslewicz, Kenneth A. Ross
openaire   +1 more source

An Isometric on on-Chip Multiprocessor Architecture

2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007
A new architecture, called isometric on-chip computer architecture (ICMA), for massive parallel computing is introduced. This architecture integrates an equal distance organization of processing elements interleaved with memory units. ICMA is inspired by the sodium chloride (NaCl) molecular structure and based on bicolor three-dimensional mesh network ...
Étienne Ogoubi, Abdelhakim Hafid, Marcel Turcotte   +2 more
openaire   +1 more source

Network caching for Chip Multiprocessors

2009 IEEE 28th International Performance Computing and Communications Conference, 2009
The large working sets of commercial and scientific workloads favor a shared L2 cache design that maximizes the aggregate cache capacity and minimizes off-chip memory requests in Chip Multiprocessors (CMP). There are two important hurdles that restrict the scalability of these chip multiprocessors: the on-chip memory cost of directory and the long L1 ...
Jinglei Wang, Yibo Xue, Haixia Wang 0001, Dongsheng Wang 0002   +3 more
openaire   +1 more source

Core-Selectability in Chip Multiprocessors

2009 18th International Conference on Parallel Architectures and Compilation Techniques, 2009
The centralized structures necessary for the extraction of instruction-level parallelism (ILP) are consuming progressively smaller portions of the total die area of chip multiprocessors (CMP). The reason for this is that scaling these structures does not enhance general performance as much as scaling the cache and interconnect.
Hashem Hashemi Najaf-abadi, Niket Kumar Choudhary, Eric Rotenberg   +2 more
openaire   +1 more source

Application mapping for chip multiprocessors

Proceedings of the 45th annual Design Automation Conference, 2008
The problem attacked in this paper is one of automatically mapping an application onto a network-on-chip (NoC) based chip multiprocessor (CMP) architecture in a locality-aware fashion. The proposed compiler approach has four major steps: task scheduling, processor mapping, data mapping, and packet routing.
Guangyu Chen, Feihui Li, Seung Woo Son 0001, Mahmut T. Kandemir   +3 more
openaire   +1 more source