Results 141 to 150 of about 441 (179)
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Utilization of cache area in on-chip multiprocessor
Microprocessors and Microsystems, 1999Abstract On-chip multiprocessor can be an alternative to the wide-issue superscalar processor approach which is currently the mainstream to exploit the increasing number of transistors on a silicon chip. Utilization of the cache, especially for the remote data is important in the system using such on-chip multiprocessors since the ratio of the off ...
Hitoshi Oi, N. Ranganathan
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Multiprocessor system-on-chip technology
IEEE Signal Processing Magazine, 2009Signal processing is a prime application for very large scale integration (VLSI) technology and systems-on-chips (SoCs), so it should be no surprise that a great deal of effort has been put into the design of architectures for signal processing. The need for programmability, real-time performance, and low-power operation are all driving factors in the ...
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1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers, 2002
Integrating processors into a chip is one of leading technologies in the microprocessor as well as in the semiconductor processing technology. This paper describes EMPC-96 which is a DBMS application-specific on-chip microprocessor for MPP systems. Four integer units, data cache, instruction cache, and system interfaces are integrated into one chip ...
null Jun-Woo Kang, null Kee-Wook Rim
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Integrating processors into a chip is one of leading technologies in the microprocessor as well as in the semiconductor processing technology. This paper describes EMPC-96 which is a DBMS application-specific on-chip microprocessor for MPP systems. Four integer units, data cache, instruction cache, and system interfaces are integrated into one chip ...
null Jun-Woo Kang, null Kee-Wook Rim
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Embedded RAIDs-on-chip for bus-based chip-multiprocessors
ACM Transactions on Embedded Computing Systems, 2014The dual effects of larger die sizes and technology scaling, combined with aggressive voltage scaling for power reduction, increase the error rates for on-chip memories. Traditional on-chip memory reliability techniques (e.g., ECC) incur significant power and performance overheads.
Luis Angel D. Bathen, Nikil D. Dutt
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GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors
10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007), 2007Due to the technological progress in the semiconductor industry, more and more components can be integrated on a single die forming a complex System-on-Chip. For enabling an efficient interaction between the various building blocks of today’s SoCs, efficient communication structures become more and more essential. In this paper, we present the GigaNoC,
Puttmann, Christoph +3 more
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CCNoC: Cache-Coherent Network on Chip for Chip Multiprocessors
Journal of Computer Science and Technology, 2010As the number of cores in chip multiprocessors (CMPs) increases, cache coherence protocol has become a key issue in integration of chip multiprocessors. Supporting cache coherence protocol in large chip multiprocessors still faces three hurdles: design complexity, performance and scalability.
Jinglei Wang +4 more
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Network-on-Chip Design for Heterogeneous Multiprocessor System-on-Chip
2014 IEEE Computer Society Annual Symposium on VLSI, 2014With burgeoning growth of mobile systems, multiprocessor System-on-Chip (MPSoC) connected via Network-on-Chip (NoC) has become ubiquitous. A typical MPSoC in mobile applications consists of multiple CPU cores of varying capabilities, GPU cores, DSP cores, and crypto accelerators and such cores differ widely in their physical size and their bandwidth ...
Bharath Phanibhushana, Sandip Kundu
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An Efficient Hybrid-Switched Network-on-Chip for Chip Multiprocessors
IEEE Transactions on Computers, 2016Chip multiprocessors (CMPs) require a low-latency interconnect fabric network-on-chip (NoC) to minimize processor stall time on instruction and data accesses that are serviced by the last-level cache (LLC). While packet-switched mesh interconnects sacrifice performance of many-core processors due to NoC-induced delays, existing circuit-switched ...
Pejman Lotfi-Kamran +2 more
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An image signal multiprocessor on a single chip
IEEE Journal of Solid-State Circuits, 1990A digital image signal multiprocessor (ISMP), a multiprocessor version of a previous real-time image signal processor (RISP) for gray-level image processing, is discussed. It is composed of a main controller and four processor elements (PEs), which are programmable 12-b digital signal processors.
Masakatsu Maruyama +6 more
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