Results 151 to 160 of about 441 (179)

Chip-level programming of heterogeneous multiprocessors

2015 10th International Design & Test Symposium (IDT), 2015
Chip Heterogeneous Multiprocessors (CHMs) are increasingly emerging as a means to optimize energy and performance over a wide spectrum of application programs. However, unlike traditional processors no programming model has been developed for CHMs. This paper proposes a set of programming primitives and benchmarking strategies for CHMs.
Mwaffaq Otoom, JoAnn M. Paul
openaire   +1 more source

Dynamic cache clustering for chip multiprocessors

Proceedings of the 23rd international conference on Supercomputing, 2009
This paper proposes DCC (Dynamic Cache Clustering), a novel distributed cache management scheme for large-scale chip multiprocessors. Using DCC, a per-core cache cluster is comprised of a number of L2 cache banks and cache clusters are constructed, expanded, and contracted dynamically to match each core's cache demand.
Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem   +2 more
openaire   +1 more source

The design of a RISC based multiprocessor chip

Proceedings SUPERCOMPUTING '90, 2002
The architecture of an RISC (reduced instruction set computer) based on multiprocessor chip designed in the Briarcliff Multiprocessor Project is described. The processors operate in an MIMD (multiple instruction, multiple data) fashion, executing parallel instruction streams generated by a parallelizing compiler for the exploitation of fine-grained ...
Rajiv Gupta 0001, Michael Epstein, Michael Whelan   +2 more
openaire   +1 more source

Write Invalidation Analysis in Chip Multiprocessors

2010
Chip multiprocessors (CMPs) issue write invalidations (WIs) to assure program correctness. In conventional snoop-based protocols, writers broadcast invalidations to all nodes as soon as possible. In this work we show that this approach, while protecting correctness, is inefficient due to two reasons.
Newsha Ardalani, Amirali Baniasadi
openaire   +1 more source

Multiprocessor Systems-on-Chips

IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006
openaire   +1 more source

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip

ACM Journal on Emerging Technologies in Computing Systems, 2012
Weichen Liu, Yaoyao Ye
exaly  

SUOR

ACM Journal on Emerging Technologies in Computing Systems, 2014
Zhe Wang, Yaoyao Ye
exaly  

Application-specific multiprocessor Systems-on-Chip

Microelectronics Journal, 2002
Gabriela Nicolescu, Amer Baghdadi, Ahmed Jerraya   +2 more
exaly  

Multiprocessor System-on-Chip (MPSoC) Technology

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008
Wayne Wolf, Ahmed Jerraya, Grant Martin   +2 more
exaly  

FONoC: A Fat Tree Based Optical Network-on-Chip for Multiprocessor System-on-Chip

Embedded Systems, 2013
Xu Jiang, Weichen Liu, Huaxi Gu
exaly