Results 131 to 140 of about 441 (179)
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Fast synchronization for chip multiprocessors
ACM SIGARCH Computer Architecture News, 2005This paper presents a novel mechanism for barrier synchronization on chip multi-processors (CMPs). By forcing the invalidation of selected I-cache lines, this mechanism starves threads and thus forces their execution to stop. Threads are let free when all have entered the barrier.We evaluated this mechanism using SMTSim and report much better (and most
Jack Sampson +4 more
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A stream chip-multiprocessor for bioinformatics
ACM SIGARCH Computer Architecture News, 2008Bioinformatics applications such as gene and protein sequence matching algorithms are characterized by the need to process large amounts of data. While uni-processor performance growth is slowing due to an increasing gap between processor and memory speeds and a saturation of processor clock frequencies, Genbank data is doubling every 15 months.
Ravi Kiran Karanam +2 more
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Migration in Single Chip Multiprocessors
IEEE Computer Architecture Letters, 2002Global communication costs in future single-chipmultiprocessors will increase linearly with distance. In this paper,we revisit the issues of locality and load balance in order totake advantage of these new costs. We present a technique whichsimultaneously migrates data and threads based on vectors specifyinglocality and resource usage.
Kelly A. Shaw 0001, William J. Dally
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Dynamic on-chip memory management for chip multiprocessors
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, 2004One of the most important issues in designing a chip multiprocessor is to decide its on-chip memory organization. A poor on-chip memory design can have serious power and performance implications when running data-intensive embedded applications. While it is possible to design an application-specific memory architecture, this may not be the best option,
Mahmut T. Kandemir +2 more
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Efficient Synchronization for Embedded On-Chip Multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2006This paper investigates optimized synchronization techniques for shared memory on-chip multiprocessors (CMPs) based on network-on-chip (NoC) and targeted at future mobile systems. The proposed solution is based on the idea of locally performing synchronization operations requiring continuous polling of a shared variable, thus, featuring large ...
Matteo Monchiero +3 more
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The future of multiprocessor systems-on-chips
Proceedings of the 41st annual Design Automation Conference, 2004This paper surveys the state-of-the-art and pending challenges in MPSoC design. Standards in communications, multimedia, networking, and other areas encourage the development of high-performance platforms that can support a range of implementations of the standard.
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Embedded Multiprocessor Systems-on-Chip Programming
IEEE Software, 2009We have demonstrated the toolflow developed at IMEC for the MPEG-4 encoder on different platforms. In the future, we want to integrate the different tools in the flow even more, because they are mainly used separately today. Furthermore, we are in the process of validating the flow on more applications, particularly in the wireless-communication domain.
Jean-Yves Mignolet, Roel Wuyts
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Adaptive Thread Scheduling in Chip Multiprocessors
International Journal of Parallel Programming, 2019The full potential of chip multiprocessors remains unexploited due to architecture oblivious thread schedulers employed in operating systems. We introduce an adaptive cache-hierarchy-aware scheduler that tries to schedule threads in a way that inter-thread contention is minimized.
Aktürk, İ., Öztürk, Özcan
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In-Network Caching for Chip Multiprocessors
2009Effective management of data is critical to the performance of emerging multi-core architectures. Our analysis of applications from SpecOMP reveal that a small fraction of shared addresses correspond to a large portion of accesses. Utilizing this observation, we propose a technique that augments a router in a on-chip network with a small data store to ...
Aditya Yanamandra +4 more
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