Results 261 to 270 of about 1,091,701 (330)

Structurally optimized SiC CMOS FinFET for high-temperature and low-power SoC logic integration. [PDF]

Sci Rep
Kwon TS, Yoon YJ, Park DY, Bae JH, Song YS, Kim HW, Seo JH, Woo SY.   +7 more
europepmc   +1 more source

A CMOS-Compatible Silicon Nanowire Array Natural Light Photodetector with On-Chip Temperature Compensation Using a PSO-BP Neural Network. [PDF]

Micromachines (Basel)
Liu M, Chen X, Zeng J, Yi J, Liu W, Qu X, Zhang J, Liu H, Liu C, Yang X, Huang K.   +10 more
europepmc   +1 more source

Wafer-scale integration of photonic integrated circuits and atomic vapor cells. [PDF]

Nanophotonics
Grosman A, Zektzer R, Mazurski N, Stern L, Levy U.   +4 more
europepmc   +1 more source

On-chip integration of achromatic metalens arrays. [PDF]

Nat Commun
Zhang Y, Jiang X, Qu G, Han J, Li C, Bo B, Ruan Q, Liu Z, Song Q, Xiao S.   +9 more
europepmc   +1 more source

Handheld Lab-on-a-Chip System for Label-Free Dual-Plex Detection of Biomarkers Through On-Chip Plasma Separation. [PDF]

Biosensors (Basel)
Chang CY, Lei YP, Chiang CC, Huang CS.
europepmc   +1 more source

Fabrication of photonic integrated circuits using high resolution CMOS fabrication process

, 2008
openaire   +2 more sources

Some of the next articles are maybe not open access.

Related searches:

CMOS-Fabricated Ring Surface Ion Trap with TSV Integration

2023 International Electron Devices Meeting (IEDM), 2023
We present the design, fabrication, and test of ring surface trap on 12-inch wafers with a CMOS process. The design is based on Through Silicon Vias (TSV) interconnects.
P. Zhao, Y. Lim, Hongyu Li, J. Likforman, Luca Guidoni, Lilay Gros Desormeaux, Chuan Seng Tan   +6 more
semanticscholar   +3 more sources

Optical characteristics of CMOS-fabricated MOSFET's

IEEE Journal of Solid-State Circuits, 1987
A CMOS fabricated MOSFET in a floating p-well on a semiconducting n-type substrate is optically sensitive and can be used for photoreception in CMOS circuitry. Experimental results for the logarithmic dependence of threshold voltage V/SUB th/ and channel current I/SUB D/ on light intensity compare well with the theory. However, the floating p-well also
S. D. Kirkish, J. Daly, L. Jou, S. Su
semanticscholar   +3 more sources

CMOS Fabricated by Hybrid-Orientation Technology (HOT)

2007 International Workshop on Electron Devices and Semiconductor Technology (EDST), 2007
Hybrid-orientation technology (HOT), a novel planar CMOS approach that fabricates NMOS on (100) silicon surface and PMOS on (110) silicon surface to take advantage of the highest carrier mobilities on these surfaces, is reviewed. HOT module process flow, defects formed during the HOT module, HOT CMOS performance enhancement and its layout dependence ...
Bin Yang, M. Yang, D. Fried, C. Sheraw, A. Waite, K. Nummy, L. Black, S. Kim, H. Yin, B. Kim, S. Narasimha, X. Chen, M. Khare, S. Luning, P. Agnello   +14 more
semanticscholar   +2 more sources

Defect cluster segmentation for CMOS fabricated wafers

2009 Innovative Technologies in Intelligent Systems and Industrial Applications, 2009
IC defects, which are essentially present in all fabricated wafers, can either be random defects or belonging to a group of systematic defects. The ability to segment systematic defects that are present in a wafer allows rapid root cause identification and corrective measures to be taken.
W. J. Tee, M. Ooi, Y. Kuang, C. Chan
semanticscholar   +2 more sources