Results 271 to 280 of about 1,091,701 (330)

Commercial CMOS fabricated integrated dynamic thermal scene simulator

International Electron Devices Meeting 1991 [Technical Digest], 1991
The authors report a prototype integrated dynamic thermal scene simulator chip, consisting of a 2*2 array of integrated thermal pixels. The chips were fabricated using commercial CMOS processes. The micromachining process needed to create the thermally isolated structure is introduced as a maskless postprocessing step. The thermal pixel and the control
M. Parameswaran, R. Chung, M. Gaitan, R. B. Johnson, M. Syrzycki   +4 more
semanticscholar   +2 more sources

Modeling and Characterization of CMOS-Fabricated Capacitive Micromachined Ultrasound Transducers

Journal of Microelectromechanical Systems, 2011
This paper describes the fabrication, characterization, and modeling of complementary metal-oxide-semiconductor (CMOS)-compatible capacitive micromachined ultrasound transducers (CMUTs). The transducers are fabricated using the interconnect and dielectric layers from a standard CMOS fabrication process.
C. B. Doody, Xiaoyang Cheng, C. A. Rich, D. Lemmerhirt, R. White   +4 more
semanticscholar   +2 more sources

CMOS-fabricated tensile Ge microstructures: towards an edge-emitting laser

2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM), 2014
The realization of a Si-integrated light source represents today the "Holy Grail" of silicon photonics. An approach based on slightly tensile strained Ge/Si heterostructures has led to the demonstration of both optically and electrically pumped laser.
G. Capellini, C. Reich, S. Guha, Y. Yamamoto, S. Lischke, J. Kreissl, L. Zimmermann, M. Virgilio, A. Ghrib, M. El Kurdi, P. Boucaud, B. Tillack, T. Schroeder   +12 more
semanticscholar   +2 more sources

High performance CMOS fabricated on hybrid substrate with different crystal orientations

IEEE International Electron Devices Meeting 2003, 2003
A novel structure and technology has been developed for high performance CMOS using hybrid silicon substrates with different crystal orientations (namely pFET on [110]-oriented surface and nFET on (100) surface) through wafer bonding and selective epitaxy.
M. Yang, M. Ieong, L. Shi, K. Chan, V. Chan, A. Chou, E. Gusev, K. Jenkins, D. Boyd, Y. Ninomiya, D. Pendleton, Y. Surpris, D. Heenan, J. Ott, K. Guarini, C. D'Emic, M. Cobb, P. Mooney, B. To, N. Rovedo, J. Benedict, R. Mo, H. Ng   +22 more
semanticscholar   +2 more sources

Ion-sensitive field-effect transistors in standard CMOS fabricated by post processing

IEEE Sensors Journal, 2002
Highly integrated ion-sensitive field-effect transistor (ISFET) microsystems require the monolithic implementation of ISFETs, CMOS electronics, and additional sensors on the same chip. This paper presents new ISFETs in standard CMOS, fabricated by post-processing of a standard CMOS VLSI chip.
C. Jakobson, U. Dinnar, M. Feinsod, Y. Nemirovsky   +3 more
semanticscholar   +2 more sources

Silicon electro-optic micro-modulator fabricated in standard CMOS technology as components for all silicon monolithic integrated optoelectronic systems

Journal of Micromechanics and Microengineering, 2021
In this paper, optoelectronic characteristics and related switching behavior of one monolithically integrated silicon light-emitting device (LED) with an interesting wavelength range of 400–900 nm are studied.
Kaikai Xu
semanticscholar   +1 more source

Multijunction thermal converters by commerical CMOS fabrication

1993 IEEE Instrumentation and Measurement Technology Conference, 2002
New multijunction thermal converters (MJTCs) fabricated in a commerical CMOS foundry are described. The MJTC is a cantilever structure with a suspended, resistance heating element and thermocouple hot junctions located near the heater on the cantilever. The pit etched below is 150 /spl times/ 150 /spl mu/m in size. The heater structure is composed of a
M. Gaitan, J. Suehle, J.R. Kinard, D.X. Huang   +3 more
openaire   +1 more source

Process simplification in deep submicron CMOS fabrication

Proceedings of International Symposium on Semiconductor Manufacturing, 2002
Process simplification in deep submicron CMOS fabrication is discussed. Process step analysis is carried out for standard 1Poly/1Metal CMOS structure, and consequently, both isolation and gate formation process are extracted as items to simplify the process. A combination of shallow trench isolation and single mask step well/gate doping is proposed for
H. Koike, H. Ohtsuka, F. Matsuoka, M. Kakumu, K. Maeguchi   +4 more
openaire   +1 more source

Nanotechnology in Silicon CMOS Fabrication and Nanoelectronics

7th. Int. Conf. on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, 2006
Summary form only given. While novel device structures using nanomaterials such as carbon nanotubes and organic molecules may be far away, there are opportunities to use nanomaterials in solving critical issues faced by silicon CMOS downscaling. Two examples, both using carbon nanotubes, in chip cooling and developing interconnects were discussed ...
A. Cassell, null Jun Li, null Quoc Ngo, C. Nguyen, null Bin Yu, M. Meyyappan   +5 more
openaire   +1 more source

Process development for CMOS fabrication using minimal fab

2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM), 2017
CMOS fabrication processes based on clean-localized technology of Minimal fab are introduced in this work. Without a cleanroom, the particle and impurities are locally controlled at each machine and wafer carrier during the fabrication process. Two methods of CMOS inverter fabrication are performed, 1) using only equipment of a minimal fab for entire ...
Sommawan Khumpuang, Kazuhiro Koga, Yongxun Liu, Shiro Kara   +3 more
openaire   +1 more source