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All-digital pulse-expansion-based CMOS digital-to-time converter
This paper presents a new all-digital CMOS digital-to-time converter (DTC) based on pulse expansion. Pulse expansion is achieved using an all-digital pulse-mixing scheme that can effectively improve the timing resolution and enable the DTC to be concise.
Chun-Chi, Chen, Che-Hsun, Chu
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Digital-to-time converter for fluorescence lifetime imaging
2013 IEEE International Instrumentation and Measurement Technology Conference (I2MTC), 2013The fluorescence lifetime property of fluorophores can be used to differentiate between spectrally identical fluorophores, to reduce background signals, and to measure ion concentration in the local environment of fluorophores. Despite these advantages, use of the technique is limited because of the high cost and low throughout of existing methods for ...
Shuo Li, Christopher D. Salthouse
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Digital-to-time converter with pulse train generation capability
2018 IEEE International Instrumentation and Measurement Technology Conference (I2MTC), 2018A new field-programmable gate array (FPGA) based digital-to-time converter (DTC) is described that has a unique feature of pulse train generation with very high resolution. As a proof of concept the DTC design was implemented in Spartan-6 FPGA device (45 nm CMOS, Xilinx).
Pawel Kwiatkowski, Ryszard Szplet
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A multi-functional arbitrary timing generator based on a digital-to-time converter
Review of Scientific Instruments, 2023This paper proposes a new high-resolution digital-to-time converter architecture based on a field programmable gate array and digital-to-analog converter (DAC). A real-time algorithm of time–-amplitude mapping is proposed, which converts the vertical resolution of the DAC to the timing resolution and realizes the ultra-high resolution timing signal ...
Dexuan Kong +3 more
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Digital-to-time converter using set in HSPICE
2015 23rd Iranian Conference on Electrical Engineering, 2015This paper presents a combination of two very important techniques in order to reduce power consumption and area. Recently a very useful method has been presented for converting digital to time in 65nm CMOS. Since Single-Electronic technology has been managed to be a novel nanoelectronic solution to reduce power consumption and area, even smaller than ...
Rahim Faez, Masoud Hakimi Heris
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Power-efficient, gate-based Digital-to-Time converter in CMOS
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017A Digital-to-Time converter (DTC) based on static CMOS multiplexers is presented, achieving a time resolution of 65 ps consuming 0.5 mW. The DTC relies on gate delay for programmability, ensuring robustness, linearity and wide delay range. Details of the transistor implementation (with sizes) is given, together with a detailed discussion on critical ...
Oystein Bjorndal, Tor Sverre Lande
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A Fractional-n subsampling PLL based on a digital-to-time converter
2016 39th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO), 2016The paper presents a subsampling PLL which uses a 10-bit, 0.5 ps unit step Digital-to-Time Converter (DTC) in the phase-error comparison path for the fractional-N lock. The gain and nonlinearity of the DTC can be digitally calibrated in the background while the PLL operates normally. During fractional multiplication of a 40 MHz reference to frequencies
Nereo Markulic +3 more
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All-Digital CMOS Time-to-Digital Converter With Temperature-Measuring Capability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020This brief presents an all-digital CMOS pulse-shrinking time-to-digital converter (TDC) with temperature-measuring capability for higher circuit value and cost saving. A pulse generator is proposed to generate either a time-added pulse or a temperature-sensing pulse. A cyclic delay line (DL) composed of a temperature-sensing DL and a pulse-shrinking DL
Chun-Chi Chen +3 more
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A digital-assistant time-to-amplitude converter with dynamic range improvement
2017 IEEE 12th International Conference on ASIC (ASICON), 2017This paper presents a DA-TAC (Digital Assistant Time amplitude Converter, TAC). Based on the concept of two-step TDC and conventional TAC, the proposed DATAC utilizes counter as coarse quantization, and fine quantization is realized by sampling the triangular signal when stop signal arrives.
Zengxin Liu +9 more
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An ULP Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter
2020 32nd International Conference on Microelectronics (ICM), 2020This paper presents a constant-slope digital-to-time converter (CS-DTC) that leverages the concepts of constant-slope charging and charge redistribution to achieve high linearity with ultra-low power consumption (ULP) that makes the proposed DTC suitable for the Internet-of-Things (IoT) applications.
Kareem R. Rashed +4 more
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