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LO Generation With a Phase Interpolator Digital-to-Time Converter
IEEE Transactions on Microwave Theory and Techniques, 2017This paper shows the generation of a local oscillator (LO) signal for cellular transceivers by means of a phase-locked loop and a phase interpolator (PI) digital-to-time converter (DTC). The PI-DTC allows arbitrary frequency shifts over a wide range.
Peter Preyler +4 more
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High resolution digital-to-time converter for low jitter digital PLLs
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2014We propose a Digial-to-Time Converter (DTC) that is capable of providing infinite-delay-over-time for application in low-jitter digital phase locked loops. The DTC is implemented using phase interpolation of quadrature phase high-speed clock signals with weight coefficients generated by direct digital synthesis.
Anil Chawda +3 more
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2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017
Based on the parallel DTCs as delay cells, a 4-bit TDC with adjustable 0.7ps∼1.4ps resolution and 11ps∼22ps dynamic range is proposed in this paper. In this design, an extremely high resolution DTC is presented, achieving 15.6fs delay per LSB. By utilizing 16 DTCs which are adjusted to have the same time interval among two neighboring DTCs, a highly ...
Tingbing Ouyang +4 more
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Based on the parallel DTCs as delay cells, a 4-bit TDC with adjustable 0.7ps∼1.4ps resolution and 11ps∼22ps dynamic range is proposed in this paper. In this design, an extremely high resolution DTC is presented, achieving 15.6fs delay per LSB. By utilizing 16 DTCs which are adjusted to have the same time interval among two neighboring DTCs, a highly ...
Tingbing Ouyang +4 more
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A Self-Calibrating Sub-Picosecond Resolution Digital-to-Time Converter
2007 IEEE/MTT-S International Microwave Symposium, 2007A novel self-calibrating high-resolution digital-to-time converter (DTC) achieves 1024 individual phase states with a resolution of 0.5 ps. The phase interpolation is done in steps, by using a cascade of coarse active delay locked line and a passive programmable fine delay.
Geetha Nagaraj +6 more
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Review of FPGA-Based Digital-to-Time Converters
2023 IEEE 16th International Conference on Electronic Measurement & Instruments (ICEMI), 2023Haoyang Dang +3 more
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A Digital-to-Time-Converter-Based Subsampling PLL for Fractional Synthesis
2019This chapter introduces an analog fractional-N subsampling PLL that relies on a digital-to-time (DTC) converter in the phase-error comparison path for fractional residue compensation. Since the DTC is put at the input of the system, its resolution, linearity, and phase noise performance introduce the bottleneck for the overall spectral purity.
Nereo Markulic +3 more
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Digital-to-Time Converter for Test Equipment Implemented Using FPGA DSP Blocks
Measurement: Journal of the International Measurement Confederation, 2021Paweł Kwiatkowski
exaly
Digital on-time generation for buck converter
2021PAHKALA JANNE MATIAS, HAURU JUHA OLAVI
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Low-Cost FPGA-Based Digital-to-Time Converter
2025 IEEE 16th Latin America Symposium on Circuits and Systems (LASCAS)Vilmondes Ribeiro Silva +2 more
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