Results 81 to 90 of about 77,045 (305)

Theoretical Upper and Lower Limits for Normalized Bandwidth of Digital Phase-Locked Loop in GNSS Receivers. [PDF]

Sensors (Basel), 2023
Song YJ, Pany T, Won JH.
europepmc   +1 more source

Steady-state probability density function of the phase error for a DPLL with an integrate-and-dump device [PDF]

The steady-state behavior of a particular type of digital phase-locked loop (DPLL) with an integrate-and-dump circuit following the phase detector is characterized in terms of the probability density function (pdf) of the phase error in the loop ...
Mileant, A., Simon, M.
core   +1 more source

Ultrafast Multilevel Switching and Synaptic Behavior in a Planar Quantum Topological Memristor

Advanced Science, EarlyView.
Dry‐transferred Bi2Te3 layers enable a planar quantum topological memristor framework. In‐plane topological surface states facilitate ultrafast & low‐power operations. Coexisting analog and digital modes support current‐controlled multilevel states. PQTM exhibits 105 s retention, 103 cycles endurance, and reproducibility across 24 devices.
Mamoon Ur Rashid, Usman Safder, Sobia Ali Khan, Anh‐Tuan Pham, Muhammad Sheeraz, Nguyen‐Hoang Dang, Duy Le Thanh, Zeeshan Tahir, Faisal Maqbool, Koo‐Hyun Chung, Sunglae Cho, Jungdae Kim, Yong Soo Kim   +12 more
wiley   +1 more source

A Background Jitter Calibration for ADCs Using TDC Phase Information From ADPLL

IEEE Access
The phase noise, commonly known as jitter, in Phase-Locked Loops (PLLs) is conventionally perceived as a stochastic process, necessitating a degree of tolerance in downstream circuits such as Analog-to-Digital Converters (ADCs). This paper addresses this
Haoyang Shen, Hao Zheng, Daniel O'Hare, Deepu John, Barry Cardiff   +4 more
doaj   +1 more source

A Design of Small Area, 0.95 mW, 612–1152 MHz Open Loop Injection-Locked Frequency Multiplier for IoT Sensor Applications

Sensors, 2018
This paper presents a 612–1152 MHz Injection-Locked Frequency Multiplier (ILFM). The proposed ILFM is used to send an input signal to a receiver in only the I/Q mismatch calibration mode. Adopting a Phase-Locked Loop (PLL) to calibrate the receiver
SungJin Kim, Dong-Gyu Kim, Chanho Kim, Dong Soo Lee, Behnam Samadpoor Rikan, YoungGun Pu, Sang-Sun Yoo, Minjae Lee, KeumCheol Hwang, Youngoo Yang, Kang-Yoon Lee   +10 more
doaj   +1 more source

Table-Based Adaptive Digital Phase-Locked Loop for GNSS Receivers Operating in Moon Exploration Missions. [PDF]

Sensors (Basel), 2022
Song YJ, Won JH.
europepmc   +1 more source

Simulation of digital phase-locked loops [PDF]

Simulation equations are developed for first and second order digital phase locked loops.
Blasche, P. R.
core   +1 more source

Compensatory Interplay Between Clarin‐1 and Clarin‐2 Deafness‐Associated Proteins Governs Phenotypic Variability in Hearing

Advanced Science, EarlyView.
Functional compensation between clarin‐1 and clarin‐2 in cochlear hair cells. Hearing loss associated with CLRN1 mutations shows striking phenotypic variability; however, the underlying mechanisms remain poorly understood. This study reveals that clarin‐1 and clarin‐2 function cooperatively in cochlear hair cells to sustain mechanoelectrical ...
Maureen Wentling, Aïda Yakhlef Sanchez, Nicolas Thelen, Müge Senarisoy, Maria Hogg, Steven Condamine, Andrea Lelli, Emilia Wysocka, Pranav Patni, Sandrine Vitry, Kerem Yasin Yildizhan, Sébastien Le Gal, Sylvie Nouaille, Michael R. Bowl, Marc Thiry, Didier Dulon, Sedigheh Delmaghani, Aziz El‐Amraoui   +17 more
wiley   +1 more source

Neural Network‐Based Permittivity Engineering of Magnetic Absorbers for Customizable Microwave Absorption

Advanced Science, EarlyView.
A neural network‐enabled permittivity engineering paradigm is introduced, transcending traditional trial‐and‐error design. By decoupling electromagnetic parameters and screening a high‐throughput feature space, an ultrathin (1.0 mm) magnetic absorber is inversely designed, experimentally achieving a superior and customizable 5.1 GHz bandwidth and ...
Chenxi Liu, Jinzhe Li, Sen Li, Zhongqiu Guo, Yao Chen, Tian Li, Renchi Qin, Jiaxu Sun, Yongxi Lu, Fanbin Meng   +9 more
wiley   +1 more source

FPGA implementation of impedance-compensated phase-locked loop for HVDC converters

The Journal of Engineering, 2018
The phase-locked loop (PLL) plays a key role in HVDC systems. Recently, a new type of PLL called the impedance-compensated phase-locked loop (IC-PLL) was introduced to compensate for the voltage drop across the AC network's Thevenin impedance, making the
Yue Yi, Ajinai Ajinai, Aniruddha M.. Gole   +2 more
doaj   +1 more source