A DRAM/SRAM memory scheme for fast packet buffers
Jorge Garcı́a-Vidal +4 more
openalex +2 more sources
Gate oxide technology relieving word-line break in 10 nm-class DRAMs [PDF]
Dongkyu Jang +9 more
openalex +1 more source
Analysis of DRAM-related proteins reveals evolutionarily conserved and divergent roles in the control of autophagy [PDF]
Jim O’Prey +3 more
openalex +1 more source
Hardware Design of DRAM Memory Prefetching Engine for General-Purpose GPUs [PDF]
Freddy Gabbay +3 more
openalex +1 more source
Predicting Optimal Power Allocation for CPU and DRAM Domains
Ananta Tiwari +2 more
openalex +2 more sources
An energy efficient processor array and memory controller for accurate processing of convolutional neural network-based inference engines. [PDF]
Deepika S, Arunachalam V.
europepmc +1 more source
High-density three-dimensional integration of dynamic random-access memory using vertical dual-gate IGZO TFTs. [PDF]
Liao F +27 more
europepmc +1 more source
Oxide Semiconductor for Advanced Memory Architectures: Atomic Layer Deposition, Key Requirement and Challenges. [PDF]
Lee CH +5 more
europepmc +1 more source

