Results 131 to 140 of about 609 (176)
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Electrostatic Discharge (ESD) and the Technology Roadmap to 2020
Pan Pacific Symposium, 2008ABSTRACT Electronic components and assemblies become more and more sensitive on electrostatic charges and fields. Till this day, one has been believed that electronic components become insensitive on ESD because of the integration of protected circuits.
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Electrostatic Discharge (ESD) and the Requirements for Personnel and Machines
Pan Pacific Symposium, 2009ABSTRACT In the past and nowadays, persons have always been the main sources of electrostatic charges. All movements and acts of persons generate electrostatic body voltages. Employees of an electronic manufacture must be aware of this.
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Challenges of electrostatic discharge (ESD) protection in emerging silicon nanowire technology
2011 9th IEEE International Conference on ASIC, 2011Electrostatic discharge (ESD) induced failures continue to be a major reliability concern in the semiconductor industry. Such a concern will in fact be intensified as the CMOS technology is scaling toward the 22-nm and beyond. This paper covers the issues and challenges pertinent to the design of electrostatic discharge (ESD) protection solutions of ...
Liou, Juin J. +4 more
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2008 9th International Conference on Solid-State and Integrated-Circuit Technology, 2008
In this paper, electrostatic discharge (ESD) protection in advanced technologies is discussed. The dilemma of ESD protection in advanced technologies and whether we will maintain the need, and desire to provide ESD protection in the future will be reviewed.
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In this paper, electrostatic discharge (ESD) protection in advanced technologies is discussed. The dilemma of ESD protection in advanced technologies and whether we will maintain the need, and desire to provide ESD protection in the future will be reviewed.
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Electrostatic Discharge (ESD) Breakdown Between a Recording Head and a Disk With an Asperity
IEEE Transactions on Magnetics, 2006The electrical breakdown behavior and damage mechanisms for a recording head flying over a charged hard disk with and without an asperity is studied. It was found that the breakdown voltage flying over a 30-nm-high asperity was as low as 1.4 V, a 50% reduction compared with a smooth disk without the asperity.
A. Wallash, H. Zhu
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Electrostatic Discharge (ESD) – Sources of Electrostatic Charge in a Production Line (SMT)
Pan Pacific Symposium, 2010ABSTRACT The number of failures caused by electrostatic discharges (ESD) has been increasing for some time now. So, it is necessary for everyone, who handles electrostatic sensitive devices (ESDS), to know the reasons of such failures. This presentation will give an overview about possible causes for ESD in a SMT production line.
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2012 IEEE International Symposium on Electromagnetic Compatibility, 2012
In this paper, we describe the modeling and simulation techniques of electrostatic discharge (ESD) events. First, the existing circuit models of the ESD generator are reviewed, and the improved model is proposed. Next, the target printed circuit board circuit is modeled, and a ground plane of the board is excited by the proposed ESD generator model ...
Tadatoshi Sekine +2 more
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In this paper, we describe the modeling and simulation techniques of electrostatic discharge (ESD) events. First, the existing circuit models of the ESD generator are reviewed, and the improved model is proposed. Next, the target printed circuit board circuit is modeled, and a ground plane of the board is excited by the proposed ESD generator model ...
Tadatoshi Sekine +2 more
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1998 IEEE International Integrated Reliability Workshop Final Report (Cat. No.98TH8363), 2002
This paper describes an ESD technology benchmarking strategy for evaluating the ESD robustness of a semiconductor technology. The strategy consists of a set of CMOS "building block" test structures, a matrix of these test structures, electrical characterization parameters, ESD metrics, a standardized failure criteria, and an extraction and testing ...
S. Voldman +6 more
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This paper describes an ESD technology benchmarking strategy for evaluating the ESD robustness of a semiconductor technology. The strategy consists of a set of CMOS "building block" test structures, a matrix of these test structures, electrical characterization parameters, ESD metrics, a standardized failure criteria, and an extraction and testing ...
S. Voldman +6 more
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Analysis of models for electrostatic discharge (ESD) and semiconductor devices
Proceedings of 1994 IEEE Industry Applications Society Annual Meeting, 2002Various models are used to simulate the electrostatic discharge (ESD) event associated with semiconductor devices; these include the human body model (HBM), the charged device model (CDM), and the field induced charged device model (FCDM). Maxwell's method is used to analyze these models to determine device potentials and the transfer of charge during ...
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Electrostatic Discharge (ESD) Failures in Thin Film Resistors
International Symposium for Testing and Failure Analysis, 1999Abstract Field failures of nichrome thin-film resistors have been investigated recently for several pieces of spaceflight hardware. These failures have involved resistance shifts ranging from a few percent to complete open circuits.
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