Results 151 to 160 of about 2,524 (188)

ESD protection device issues for IC designs

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169), 2002
Electrostatic discharge (ESD) has been a major concern for IC chip quality. In this paper, the IC damage phenomena due to ESD and the protection techniques are reviewed. Also, the severe impact of the advanced process technologies on the ESD robustness, and the special circuit requirements that make the protection design even more challenging will be ...
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A new design for complete on-chip ESD protection

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044), 2002
The design of a novel compact Electrostatic Discharge (ESD) protection structure is reported. It provides complete ESD protection in all directions, i.e. positive/negative from I/O to power supply V/sub DD/, positive/negative from I/O to ground, and from V/sub DD/ to ground.
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Recent developments in ESD protection for RF ICs

Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC, 2003
New challenge in ESD protection design for RF ICs is to address the complex interactions between the ESD protection network and the core circuit being protected in both directions. This paper reviews recent developments in RF ESD protection design, including switching and mis-triggering of ESD protection networks; ESD-induced parasitic capacitive ...
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RC-diode ESD protection design for high-frequency applications

Solid-State Electronics, 2022
Chun-Yu Lin
exaly  

Design strategies for ESD protection in SOC

4th IEEE International Workshop on System-on-Chip for Real-Time Applications, 2004
Krzysztof Iniewski, Valery Axelrad, Andrei Shibkov, Artur Balasinski, Marek Syrzycki   +4 more
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Advances in ESD protection for ICs

Microelectronics Reliability, 2013
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ESD Protection Designs: Topical Overview and Perspective

IEEE Transactions on Device and Materials Reliability, 2022
Zijin Pan, Weiquan Hao, Xunyu Li
exaly  

Arrangement and method for ESD protection

2004
An arrangement (200) and method for scalable ESD protection of a semiconductor structure (140), a protection structure (120) providing a discharge transistor (110) path from an input/output node (130) to ground or another node if a threshold voltage is reached, wherein the discharge transistor is a self-triggered transistor having collector/drain (220)
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A Review on RF ESD Protection Design

IEEE Transactions on Electron Devices, 2005
A Z H Wang, Haigang Feng, Rouying Zhan   +2 more
exaly  

Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI

IEEE Transactions on Electron Devices, 1999
Ming-Dou Ker
exaly