Results 141 to 150 of about 2,524 (188)

ESD protection in finfet technologies

IEEE 2011 International SOI Conference, 2011
▸ Strong dependency on - process technology (SOIFF, bulkFF) - process options (strain, SEG,…) - layout parameters (L G , W fin ,…) ▸ ESD needs to be considered early during technology development ▸ ESD remains very challenging but ▸ ESD is no roadblock for the introduction of both SOIFF and bulkFF!
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Comparison of ESD protection effect between protective elements on electric devices and ESD countermeasure materials by applying voltage with ESD gun

2015 Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC), 2015
The purpose of this study is to support the countermeasure technology in the system level by using the developed observation system. It can observe a discharge current waveform, a discharge voltage waveform and a radiated electromagnetic waveform to make comparison of ESD protection effect between protective elements on electric devices and ESD ...
Takayoshi Ohtsu, Hideyuki Doyama, Hiroyasu Ishizuka, Kouichi Sagisaka   +3 more
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ESD protection solutions for high voltage technologies

Microelectronics Reliability, 2004
There is a trend to revive mature technologies while including high voltage options. ESD protection in those technologies is challenging due to narrow ESD design windows, NMOS degradation issues and the creation of unexpectedly weak parasitic devices. Different case studies are presented for ESD protection based on latch-up immune SCR devices.
Bart Keppens, Markus P. J. Mergens, Cong Son Trinh, Christian C. Russ, Benjamin Van Camp, Koen G. Verhaege   +5 more
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A novel gate-suppression technique for ESD protection

Microelectronics Reliability, 2012
Abstract A novel gate-suppression technique derived from source-pumping technique is proposed for Electrostatic Discharge (ESD) protection application. By employing the complementary SCR structure, an improved source-pumping and the gate-suppression scheme are able to extend ESD window and endure a high level of ESD impact without additional layout ...
Meng Miao, Shurong Dong, Mingliang Li, Jian Wu 0004, Fei Ma, Jianfeng Zheng, Yan Han 0005   +6 more
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Esd protection circuit

2008
An electro-static discharge protection circuit including: a first input terminal and a second input terminal; a first output terminal coupled to the first input terminal, and a second output terminal coupled to the second input terminal; a first circuit branch connected between the first input terminal and the second input terminal, said first circuit ...
Giuseppe Consentino, Gaetano Bazzano, Antonio Grimaldi, Monica Miccichè   +3 more
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Co-design of ESD protection and LNA in RFIC

2013 IEEE 10th International Conference on ASIC, 2013
This paper introduces a new FoM (figure of merit) to evaluate the overall performance of ESD and LNA and presents a design procedure of establishing a standard library of ESD protection cells to reduce the design time and complexity for RFIC designer. The electrostatic discharge protection cells have been designed in a 0.35µm BiCMOS process.
Yueguo Hao, Qiao Zhang, Xiaopeng Bai, Zitao Shi, Huainan Ma, Yuhua Cheng   +5 more
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An ESD protection circuit for mixed-signal ICs

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169), 2002
A new ESD (electrostatic discharge) protection circuit was designed and implemented in commercial BiCMOS. One such ESD unit is adequate for each I/O pin to survive ESD stressing of all modes. This novel ESD circuit features adjustable low-trigger-voltage, symmetric active discharge channels in all directions, fast response, and high ESD performance ...
Haigang Feng, Ke Gong, Albert Z. Wang
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Field programmable SONOS ESD protection design

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
This paper reports the first SONOS-based field-programmable ESD protection concept and structure. Prototype in 130nm CMOS demonstrates wide ESD triggering tuning range of ∼2V and ultra low leakage of 1.2pA. It enables post-Si on-chip/in-system ESD design programmability for complex ICs.
Jian Liu 0027, Zitao Shi, Xin Wang 0031, Hui Zhao 0014, L. Wang, Chen Zhang 0017, Zongyu Dong, L. Lin, Albert Z. Wang, Yuhua Cheng, Bin Zhao 0002   +10 more
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ESD protection networks for 3D integrated circuits

2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International, 2012
The inter-die signal interfaces in a 3D-IC are vulnerable to over-voltage stress induced by Charged Device Model ESD. The magnitude of the stress is highly sensitive to the design of the ground distribution network on both the die and package level. It is also affected by the type of package being used.
Elyse Rosenbaum, Vrashank Shukla, Min-Sun Keel   +2 more
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Méthodologies de protection ESD

2018
Les défaillances induites par les décharges électrostatiques (ESD) constituent un problème majeur de fiabilité et de robustesse des circuits intégrés et des systèmes électroniques.Dans certaines applications comme celles de l’automobile, ce pourcentage peut être proche de 20 %.
Marise Bafleur, Fabrice Caignet, Nicolas Nolhier   +2 more
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