Results 1 to 10 of about 71,373 (192)
A Flexible Pulse Generator Based on a Field Programmable Gate Array Architecture for Functional Electrical Stimulation [PDF]
Front Neurosci, 2022 Jorge A. Mercado-Gutiérrez +6 more
openalex +2 more sources
Diffuse Correlation Spectroscopy Analysis Implemented on a Field Programmable Gate Array [PDF]
IEEE Access, 2019 Wei Lin +4 more
openalex +2 more sources
Soil moisture monitoring using field programmable gate array [PDF]
, 2018 This paper presents a solution for remote monitoring and sensing of different agricultural parameters that effect the plant growth and productivity.
Hamzah, Shipun Anuar +5 more
core +4 more sources
Programmable Logic Devices in Experimental Quantum Optics [PDF]
, 2002 We discuss the unique capabilities of programmable logic devices (PLD's) for experimental quantum optics and describe basic procedures of design and implementation.
Andrews +12 more
core +2 more sources
A field programmable gate array based modular motion control platform [PDF]
, 2011 The expectations from motion control systems have been rising day by day. As the systems become more complex, conventional motion control systems can not achieve to meet all the specifications with optimized results.
Koc, Osman +5 more
core +1 more source
A low-power reconfigurable logic array based on double-gate transistors [PDF]
, 2008 A fine-grained reconfigurable architecture based on double gate technology is proposed and analyzed. The logic function operating on the first gate of a double-gate (DG) transistor is reconfigured by altering the charge on its second gate.
Beckett, P
core +1 more source
Field Programmable Gate Array [PDF]
, 2017 In this chapter, we describe the design of a field programmable gate array (FPGA) board capable of acquiring the information coming from a fast digitization of the signals generated in a drift chambers. The digitized signals are analyzed using an ad hoc real‐time algorithm implemented in the FPGA in order to reduce the data throughput coming from the ...
Gianluigi Chiarello +6 more
openaire +3 more sources
A parallel Viterbi decoder for block cyclic and convolution codes [PDF]
, 2005 We present a parallel version of Viterbi's decoding procedure, for which we are able to demonstrate that the resultant task graph has restricted complexity in that the number of communications to or from any processor cannot exceed 4 for BCH codes.
Amarasinghe, Kosala, Reeve, Jeffrey
core +2 more sources
Statistical lossless compression of space imagery and general data in a reconfigurable architecture [PDF]
, 2008 This paper investigates an universal algorithm and hardware architecture for context-based statistical lossless compression of multiple types of data using FPGA (Field Programmable Gate Array) devices which support partial and dynamic reconfiguration ...
Canagarajah, CN +3 more
core +2 more sources