Results 11 to 20 of about 71,482 (292)
Field Programmable Gate Array [PDF]
In this chapter, we describe the design of a field programmable gate array (FPGA) board capable of acquiring the information coming from a fast digitization of the signals generated in a drift chambers. The digitized signals are analyzed using an ad hoc real‐time algorithm implemented in the FPGA in order to reduce the data throughput coming from the ...
Gianluigi Chiarello +6 more
openaire +3 more sources
This paper presents a proposal for a four-context programmable optically reconfigurable gate array (PORGA) with a high-resolution reflective silver-halide holographic memory and a corresponding writer system.
Shinya Kubota, Minoru Watanabe
doaj +1 more source
The objective of this article is to build a field programmable gate array–based six-axis servo control integrated chip which can integrate the function of a motion trajectory planning and the function of six position/speed/current servo controllers into ...
Ying-Shieh Kung +3 more
doaj +1 more source
Parallelized Particle Swarm Optimization on FPGA for Realtime Ballistic Target Tracking
This paper addresses the problem of tracking a high-speed ballistic target in real time. Particle swarm optimization (PSO) can be a solution to overcome the motion of the ballistic target and the nonlinearity of the measurement model. However, in general,
Juhyeon Park +4 more
doaj +1 more source
Vision-based object tracking has lots of applications in robotics, like surveillance, navigation, motion capturing, and so on. However, the existing object tracking systems still suffer from the challenging problem of high computation consumption in the ...
Congyi Lyu +4 more
doaj +1 more source
A Field Programmable Gate Array (FPGA) Based Non-Linear Filters for Gas Turbine Prognostics
The removal of noise from signals obtained through the health monitoring systems in gas turbines is an important consideration for accurate prognostics.
Jayant Kumar Nayak +2 more
doaj +1 more source
A parallel Viterbi decoder for block cyclic and convolution codes [PDF]
We present a parallel version of Viterbi's decoding procedure, for which we are able to demonstrate that the resultant task graph has restricted complexity in that the number of communications to or from any processor cannot exceed 4 for BCH codes.
Amarasinghe, Kosala, Reeve, Jeffrey
core +2 more sources
Implementing EW Receivers Based on Large Point Reconfigured FFT on FPGA Platforms [PDF]
This paper presents design and implementation of digital receiver based on large point fast Fourier transform (FFT) suitable for electronic warfare (EW) applications.
He Chen +3 more
doaj +1 more source
Statistical lossless compression of space imagery and general data in a reconfigurable architecture [PDF]
This paper investigates an universal algorithm and hardware architecture for context-based statistical lossless compression of multiple types of data using FPGA (Field Programmable Gate Array) devices which support partial and dynamic reconfiguration ...
Canagarajah, CN +3 more
core +2 more sources
Implementation of fractional order integrator/differentiator on field programmable gate array
Concept of fractional order calculus is as old as the regular calculus. With the advent of high speed and cost effective computing power, now it is possible to model the real world control and signal processing problems using fractional order calculus ...
K.P.S. Rana +3 more
doaj +1 more source

