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Fingerprinting Field Programmable Gate Arrays
2017 IEEE International Conference on Computer Design (ICCD), 2017The semiconductor industry has adopted a horizontal business model wherein one company designs the Integrated Circuits (ICs), a second company fabricates them and a third one tests and packages them. Separating design from fabrication introduces vulnerabilities in the IC supply chain.
Vinayaka Jyothi +3 more
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An architecture for a DSP field-programmable gate array
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1995This paper describes an application specific architecture for field-programmable gate arrays (FPGAs). Emphasis is placed on the logic module architecture and channel segmentation for the FPGAs targeted for application areas related to digital signal processing (DSP).
M. Agarwala, Poras T. Balsara
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2021
Field-programmable gate arrays (FPGAs) are integrated circuits whose logic and their interconnections are configurable. These devices are field-programmable, that is, they can be configured by the hardware designer without any intervention of the manufacturer.
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Field-programmable gate arrays (FPGAs) are integrated circuits whose logic and their interconnections are configurable. These devices are field-programmable, that is, they can be configured by the hardware designer without any intervention of the manufacturer.
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On routability prediction for field-programmable gate arrays
Proceedings of the 30th international on Design automation conference - DAC '93, 1993Efficient utilization of Field Programmable Gate Arrays (FPGAs) depends on the ability to determine whether designs will exceed the logic or routing capacities of the devices. Here, we focus on the problem of assessing the routability of designs for FPGAs before place-and-route.
Pak K. Chan +2 more
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Image processing on Field Programmable Gate Arrays
2015 23nd Signal Processing and Communications Applications Conference (SIU), 2015At present, the relevancy to image processing is increasing and applications of image processing are developing. Also “Field Programmable Gate Arrays (FPGA)” is gaining in popularity nowadays. FPGAs are strong in parallel computation and then can work too fast.
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Activity Estimation for Field-Programmable Gate Arrays
2006 International Conference on Field Programmable Logic and Applications, 2006This paper examines various activity estimation techniques in order to determine which are most appropriate for use in the context of field-programmable gate arrays (FPGAs). Specifically, the paper compares how different activity estimation techniques affect the accuracy of FPGA power models and the ability of power-aware FPGA CAD tools to minimize ...
Julien Lamoureux, Steven J. E. Wilton
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Synthesis method for field programmable gate arrays
Proceedings of the IEEE, 1993Logic synthesis algorithms and methods for field-programmable gate arrays (FPGAs) are reviewed. The three most popular types of FPGA architectures are considered, namely, those using logic blocks based on lookup-tables, multiplexers, and wide AND/OR arrays, respectively.
Alberto L. Sangiovanni-Vincentelli +2 more
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Field Programmable Gate Arrays
2019The chapter deals with field-programmable gate arrays (FPGA). The basic stages are shown concerning evolution of programmable logic (from PROMs and PLAs to FPGAs). Next, the evolution of FPGAs is analysed. Three ages of FPGAs are shown. Next, the modern FPGAs produced by Xilinx and Intel (Altera) The last section is devoted to design methods targeting ...
Alexander Barkalov +2 more
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Logic synthesis for field-programmable gate arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994In this paper, we consider the problem of configuring Field Programmable Gate Arrays (FPGA's) so that some given function is computed by the device. Obtaining the information necessary to configure a FPGA entails both logic synthesis and logic embedding.
TingTing Hwang +3 more
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Implementing division with field programmable gate arrays
Journal of VLSI signal processing systems for signal, image and video technology, 1994This article presents a method to map digit-recurrence arithmetic algorithms to lookup-table based Field Programmable Gate Arrays (FPGAs). By reducing the number of binary inputs to combinational logic and merging algorithm steps, the strategy creates new simplified functions to decrease logic depth and area.
Marianne E. Louie, Milos D. Ercegovac
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