Results 21 to 30 of about 46,893 (234)

PROGRAPE-1: A Programmable, Multi-Purpose Computer for Many-Body Simulations [PDF]

, 1999
We have developed PROGRAPE-1 (PROgrammable GRAPE-1), a programmable multi-purpose computer for many-body simulations. The main difference between PROGRAPE-1 and "traditional" GRAPE systems is that the former uses FPGA (Field Programmable Gate Array ...
Fukushige, Toshiyuki, Hamada, Tsuyoshi, Kawai, Atsushi, Makino, Junichiro   +3 more
core   +4 more sources

Development of field programmable gate array–based encryption module to mitigate man-in-the-middle attack for nuclear power plant data communication network

Nuclear Engineering and Technology, 2018
This article presents a security module based on a field programmable gate array (FPGA) to mitigate man-in-the-middle cyber attacks. Nowadays, the FPGA is considered to be the state of the art in nuclear power plants I&C systems due to its flexibility ...
Mohamed Abdallah Elakrat, Jae Cheon Jung
doaj   +1 more source

Josephson Junction Model: FPGA Implementation and Chaos-Based Encryption of sEMG Signal through Image Encryption Technique

Complexity, 2022
The field programmable gate array (FPGA) implementation of the nonlinear resistor-capacitor-inductor shunted Josephson junction (NRCISJJ) model and its application to sEMG (Surface ElectroMyoGraphic) signal encryption through image encrypted technique ...
Colince Welba, Dhanagopal Ramachandran, Alexendre Noura, Victor Kamdoum Tamba, Sifeu Takougang Kingni, Pascal Eloundou Ntsama, Pierre Ele   +6 more
doaj   +1 more source

Parallelized Particle Swarm Optimization on FPGA for Realtime Ballistic Target Tracking

Sensors, 2023
This paper addresses the problem of tracking a high-speed ballistic target in real time. Particle swarm optimization (PSO) can be a solution to overcome the motion of the ballistic target and the nonlinearity of the measurement model. However, in general,
Juhyeon Park, Heoncheol Lee, Hyuck-Hoon Kwon, Yeji Hwang, Wonseok Choi   +4 more
doaj   +1 more source

Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET

, 2011
Scalability of Field Programmable Gate Array (FPGA) using spin MOSFET (spin FPGA) with magnetocurrent (MC) ratio in the range of 100% to 1000% is discussed for the first time. Area and speed of million-gate spin FPGA are numerically benchmarked with CMOS
Gao Y., Hideyuki Sugiyama, Inokuchi T., Kazutaka Ikegami, Marukame T., Mizue Ishikawa, Nagamine Y., Sugiyama H., Takao Marukame, Tetsufumi Tanamoto, Tomoaki Inokuchi, Yoshiaki Saito   +11 more
core   +1 more source

Dynamic reconfiguration technologies based on FPGA in software defined radio system [PDF]

, 2011
Partial Reconfiguration (PR) is a method for Field Programmable Gate Array (FPGA) designs which allows multiple applications to time-share a portion of an FPGA while the rest of the device continues to operate unaffected.
Ke He, Louise Crockett, Robert Stewart, W Tuttlebee   +3 more
core   +2 more sources

High Level Implementation Methodologies of DSP Module using FPGA and System Generator [PDF]

Engineering and Technology Journal, 2016
This paper presents the high level implementation methodologies of Digital Signal Processing (DSP) module by using the Field Programmable Gate Array (FPGA) andintegrated software environments (ISE) with the System Generator programs.
Majid S. Naghmash, Mousa K. Wali, Amar A. Abdulmajeed   +2 more
doaj   +1 more source

A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs) [PDF]

Sensors, 2013
This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations.
Gomez Osuna, Carlos, Ituero Herrero, Pablo, López Vallejo, Marisa   +2 more
openaire   +4 more sources

Sequential Discrete Kalman Filter for Real-Time State Estimation in Power Distribution Systems: Theory and Implementation

, 2017
This paper demonstrates the feasibility of implementing Real-Time State Estimators (RTSEs) for Active Distribution Networks (ADNs) in Field-Programmable Gate Arrays (FPGAs) by presenting an operational prototype.
Kettner, Andreas Martin, Paolone, Mario
core   +1 more source

Data Packet Processing Acceleration Architecture for Virtual Network Function Based on FPGA [PDF]

Jisuanji gongcheng, 2018
In order to improve the packet processing performance of Virtual Network Function(VNF),this paper comes up with a Field Programmable Gate Array(FPGA)-based General Hardware Accelerator(GHA) architecture.The GHA architecture implements the packet ...
FAN Hongwei,HU Yuxiang,LAN Julong
doaj   +1 more source