Results 31 to 40 of about 46,893 (234)
Complexity Analysis of MMSE Detector Architectures for MIMO OFDM Systems [PDF]
, 2005 In this paper, a field programmable gate array (FPGA) implementation of a linear minimum mean square error (LMMSE) detector is considered for MIMO-OFDM systems.
Byman, Aaron +5 more
core +1 more source
The use of field-programmable gate arrays for the hardware acceleration of design automation tasks [PDF]
, 1996 This paper investigates the possibility of using Field-Programmable Gate Arrays (Fr’GAS) as reconfigurable co-processors for workstations to produce moderate speedups for most tasks in the design process, resulting in a worthwhile overall design ...
Allinson, Nigel M. +2 more
core +2 more sources
Real‐Time 3D Ultrasound Imaging with an Ultra‐Sparse, Low Power Architecture
Advanced Healthcare Materials, EarlyView.This article presents a novel, ultra‐sparse ultrasound architecture that paves the way for wearable real‐time 3D imaging. By integrating a unique convolutional array with chirped data acquisition, the system achieves high‐resolution volumetric scans at a fraction of the power and hardware complexity.
Colin Marcus +9 more
wiley +1 more source
Observation of Dislocation Bound States and Skin Effects in Non‐Hermitian Chern Insulators
Advanced Materials, EarlyView.Experimental observation of the dislocation‐induced bound states and skin effects is demonstrated in a line‐gap non‐Hermitian acoustic lattice. By utilizing active meta‐atoms to measure the full complex spectrum and biorthogonal eigenstates, the study reveals the exceptional‐point‐driven melting of defect modes.
Jia‐Xin Zhong, Bitan Roy, Yun Jing
wiley +1 more source
Multiband Real-Time Coherent Optical OFDM Reception up to 110 Gb/s with 600-km Transmission
IEEE Photonics Journal, 2010 We demonstrate field-programmable gate array (FPGA)-based multiband orthogonal frequency-division multiplexing (OFDM) signal reception after 600-km standard single-mode fiber (SSMF) transmission and 400-ps differential-group delay (DGD) at 110-Gb/s.
Simin Chen, Yiran Ma, William Shieh
doaj +1 more source
FPGA Implementation of A∗ Algorithm for Real-Time Path Planning
International Journal of Reconfigurable Computing, 2020 The traditional A∗ algorithm is time-consuming due to a large number of iteration operations to calculate the evaluation function and sort the OPEN list.
Yuzhi Zhou, Xi Jin, Tianqi Wang
doaj +1 more source
LISA phasemeter development: Advanced prototyping [PDF]
, 2009 We present the status of our investigations on the LISA Phasemeter. The new prototype is based on a custom-designed breadboard with four high-speed ADC and two DAC channels, extended readout capabilities and a large FPGA (field programmable gate array ...
Bykov, Iouri +4 more
core +2 more sources
Advanced Science, EarlyView.An on‐demand ultra‐reconfigurable intelligent vision system with hierarchical reconfigurability from device to system levels is demonstrated. Through co‐design of a multi‐paradigm device, reconfigurable circuits, and adaptive system architecture/algorithms, the system enables seamless switching among spiking, non‐spiking, neuromorphic imaging (NI), and
Biyi Jiang +7 more
wiley +1 more source
Advances in Mechanical Engineering, 2013 This paper presents an intelligent motion controller for four-wheeled holonomic mobile robots with four driving omnidirectional wheels equally spaced at 90 degrees from one another by using field-programmable gate array (FPGA)-based artificial immune ...
Hsu-Chih Huang
doaj +1 more source
Journal of King Saud University: Engineering Sciences, 2009 Histogram projection (HP) is a well-suited enhancement technique for images obtained by uncooled infrared imagers. In this paper, the problem of implementing HP using Field Programmable Gate Array (FPGA) is addressed.The proposed system is implemented ...
A.M. Alsuwailem
doaj +1 more source