Results 31 to 40 of about 91,286 (241)

Field Programmable Gate Array Applications - A Scientometric Review

open access: yesDe Computis, 2019
Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems.
Juan Ruiz-Rosero   +2 more
semanticscholar   +1 more source

High Level Implementation Methodologies of DSP Module using FPGA and System Generator [PDF]

open access: yesEngineering and Technology Journal, 2016
This paper presents the high level implementation methodologies of Digital Signal Processing (DSP) module by using the Field Programmable Gate Array (FPGA) andintegrated software environments (ISE) with the System Generator programs.
Majid S. Naghmash   +2 more
doaj   +1 more source

A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs) [PDF]

open access: yesSensors, 2013
This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations.
Gomez Osuna, Carlos   +2 more
openaire   +4 more sources

Experimental Investigation on the Performances of a Multilevel Inverter Using a Field Programmable Gate Array-Based Control System

open access: yesEnergies, 2019
The Field Programmable Gate Array (FPGA) represents a valid solution for the design of control systems for inverters adopted in many industry applications, because of both its high flexibility of use and its high-performance with respect to other types ...
G. Ala   +6 more
semanticscholar   +1 more source

The use of field-programmable gate arrays for the hardware acceleration of design automation tasks [PDF]

open access: yes, 1996
This paper investigates the possibility of using Field-Programmable Gate Arrays (Fr’GAS) as reconfigurable co-processors for workstations to produce moderate speedups for most tasks in the design process, resulting in a worthwhile overall design ...
Allinson, Nigel M.   +2 more
core   +2 more sources

Sequential Discrete Kalman Filter for Real-Time State Estimation in Power Distribution Systems: Theory and Implementation

open access: yes, 2017
This paper demonstrates the feasibility of implementing Real-Time State Estimators (RTSEs) for Active Distribution Networks (ADNs) in Field-Programmable Gate Arrays (FPGAs) by presenting an operational prototype.
Kettner, Andreas Martin, Paolone, Mario
core   +1 more source

Data Packet Processing Acceleration Architecture for Virtual Network Function Based on FPGA [PDF]

open access: yesJisuanji gongcheng, 2018
In order to improve the packet processing performance of Virtual Network Function(VNF),this paper comes up with a Field Programmable Gate Array(FPGA)-based General Hardware Accelerator(GHA) architecture.The GHA architecture implements the packet ...
FAN Hongwei,HU Yuxiang,LAN Julong
doaj   +1 more source

Complexity Analysis of MMSE Detector Architectures for MIMO OFDM Systems [PDF]

open access: yes, 2005
In this paper, a field programmable gate array (FPGA) implementation of a linear minimum mean square error (LMMSE) detector is considered for MIMO-OFDM systems.
Byman, Aaron   +5 more
core   +1 more source

Multiband Real-Time Coherent Optical OFDM Reception up to 110 Gb/s with 600-km Transmission

open access: yesIEEE Photonics Journal, 2010
We demonstrate field-programmable gate array (FPGA)-based multiband orthogonal frequency-division multiplexing (OFDM) signal reception after 600-km standard single-mode fiber (SSMF) transmission and 400-ps differential-group delay (DGD) at 110-Gb/s.
Simin Chen, Yiran Ma, William Shieh
doaj   +1 more source

FPGA Implementation of A∗ Algorithm for Real-Time Path Planning

open access: yesInternational Journal of Reconfigurable Computing, 2020
The traditional A∗ algorithm is time-consuming due to a large number of iteration operations to calculate the evaluation function and sort the OPEN list.
Yuzhi Zhou, Xi Jin, Tianqi Wang
doaj   +1 more source

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