Results 1 to 10 of about 85,934 (320)

Switching performance assessment of gate-all-around InAs–Si vertical TFET with triple metal gate, a simulation study [PDF]

open access: diamondDiscover Nano, 2023
This study presents a gate-all-around InAs–Si vertical tunnel field-effect transistor with a triple metal gate (VTG-TFET). We obtained improved switching characteristics for the proposed design because of the improved electrostatic control on the channel
Dariush Madadi, Saeed Mohammadi
doaj   +4 more sources

Quantum transport through a constriction in nanosheet gate-all-around transistors [PDF]

open access: diamondCommunications Engineering
In nanoscale transistors, quantum mechanical effects such as tunneling and quantization significantly influence device characteristics. However, large-scale quantum transport simulation remains a challenging field, making it difficult to account for ...
Kyoung Yeon Kim   +5 more
doaj   +4 more sources

A Review of Reliability in Gate-All-Around Nanosheet Devices [PDF]

open access: yesMicromachines
The gate-all-around (GAA) nanosheet (NS) field-effect-transistor (FET) is poised to replace FinFET in the 3 nm CMOS technology node and beyond, marking the second seminal shift in device architecture across the extensive 60-plus-year history of MOSFET ...
Miaomiao Wang
doaj   +4 more sources

Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices [PDF]

open access: yesNanomaterials, 2021
In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated.
Qingzhu Zhang   +18 more
doaj   +4 more sources

4-Levels Vertically Stacked SiGe Channel Nanowires Gate-All-Around Transistor with Novel Channel Releasing and Source and Drain Silicide Process [PDF]

open access: yesNanomaterials, 2022
In this paper, the fabrication and electrical performance optimization of a four-levels vertically stacked Si0.7Ge0.3 channel nanowires gate-all-around transistor are explored in detail. First, a high crystalline quality and uniform stacked Si0.7Ge0.3/Si
Xiaohong Cheng   +9 more
doaj   +2 more sources

Implementation of Gate-All-Around Gate-Engineered Charge Plasma Nanowire FET-Based Common Source Amplifier [PDF]

open access: yesMicromachines, 2023
This paper examines the performance of a Gate-Engineered Gate-All-Around Charge Plasma Nanowire Field Effect Transistor (GAA-DMG-GS-CP NW-FET) and the implementation of a common source (CS) amplifier circuit.
Sarabdeep Singh   +5 more
doaj   +2 more sources

Germanium Gate-All-Around FETs on SOI [PDF]

open access: bronzeECS Meeting Abstracts, 2012
Abstract not Available.
Hung-Chih Chang   +7 more
openaire   +2 more sources

Improving the Performance of Arsenene Nanoribbon Gate-All-Around Tunnel Field-Effect Transistors Using H Defects [PDF]

open access: yesNanomaterials
We systematically study the transport properties of arsenene nanoribbon tunneling field-effect transistors (TFETs) along the armchair directions using first-principles calculations based on density functional theory combined with the non-equilibrium ...
Shun Song   +5 more
doaj   +2 more sources

Stacked Nanosheet Gate‐All‐Around Morphotropic Phase Boundary Field‐Effect Transistors [PDF]

open access: yesAdvanced Science
A material design method is proposed using ferroelectric (FE)–antiferroelectric (AFE) mixed‐phase HfZrO2 (HZO) to achieve performance improvements in morphotropic phase boundary (MPB) field‐effect transistors (MPB‐FETs), such as steep subthreshold swing (
Sihyun Kim   +3 more
doaj   +2 more sources

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