Results 21 to 30 of about 18,442,244 (245)
Narrow Sub-Fin Technique for Suppressing Parasitic-Channel Effect in Stacked Nanosheet Transistors
IEEE Journal of the Electron Devices Society, 2022 A new approach of narrowing sub-fin with little extra process cost for suppressing parasitic-channel-effect (PCE) on vertically-stacked horizontal gate-all-around (GAA) Si nanosheet field-effect-transistors (NS-FETs) is proposed.
Jie Gu +11 more
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IEEE Journal of the Electron Devices Society, 2021 This study investigates a device’s ability to boost its on-state current and subthreshold behavior using a ferroelectric field-effect transistor (FeFET) with an ultrathin sub-5-nm Hf1-xZrxO2 (HZO). A conventional field-effect transistor (FET) with
Shen-Yang Lee +4 more
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IEEE Journal of the Electron Devices Society, 2019 Present work demonstrates the vertically double stacked nanosheet (NS) p-channel polycrystalline silicon (poly-Si) junctionless field-effect transistors (JL-FET) with tri-gate, omega-gate, and gate all around (GAA) structure.
Meng-Ju Tsai +7 more
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IEEE Journal of the Electron Devices Society, 2021 For improving self-heating effects (SHEs) in gate-all-around metal-oxide-semiconductor field-effect transistors (GAA MOSFETs), hetero-gate-dielectric (HGD) is utilized. The HGD consists of hafnium dioxide (HfO2) and silicon dioxide (SiO2), which has high
Young Suh Song +5 more
doaj +1 more source
NEGF simulations of a junctionless Si gate-all-around nanowire transistor with discrete dopants [PDF]
, 2012 We have carried out 3D Non-Equilibrium Green Function simulations of ajunctionlessgate-all-around n-type silicon nanowiretransistor of 4.2 × 4.2 nm2 cross-section. We model the dopants in a fully atomistic way.
Brown, A. +10 more
core +1 more source
A comparison of electrical performance analysis between nanoscale double-gate and gate-all-around nanowire mosfet [PDF]
, 2020 The Double-Gate and Gate-all-Around are said to be the promising candidates to pursue Complementary-Metal-Oxide Semiconductor scaling. When the device is scaled down, several problems arise such as the short-channel effect, excessive transistor ...
Kosmani, Nor Fareza
core +1 more source
Performance of Stacked Nanosheets Gate-All-Around and Multi-Gate Thin-Film-Transistors
IEEE Journal of the Electron Devices Society, 2018 This comprehensive study of the horizontally p-type stacked nanosheets inversion mode thinfilm transistor with gate-all-around (SNS-GAATFT) and multi-gate (SNS-TFT) structures.
Yu-Ru Lin +6 more
doaj +1 more source
Nanoscale Research Letters, 2022 This work reports an emerging structure of gate-all-around ferroelectric area tunneling field-effect transistor (FATFET) by considering ferroelectric and a n-epitaxial layer enveloped around the overlapped region of the source and channel to succeed with
Narasimhulu Thoti, Yiming Li
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Power Reduction in Punch-Through Current-Based Electro-Thermal Annealing in Gate-All-Around FETs. [PDF]
Micromachines (Basel), 2022 Device guidelines for reducing power with punch-through current annealing in gate-all-around (GAA) FETs were investigated based on three-dimensional (3D) simulations.
Kim MK, Choi YK, Park JY.
europepmc +2 more sources
A comparison of performance between double-gate and gate-all-around nanowire mosfet [PDF]
, 2019 Due to the rapid scaling of Complementary Metal-Oxide-Semiconductor (CMOS), the structure of the planar MOSFET approaches the scaling limits when the short channel effects (SCEs) become the main problem.
Hamid, Fatimah A. +4 more
core +1 more source