Results 21 to 30 of about 12,503,659 (299)

Ultrathin Sub-5-nm Hf₁₋ₓZrₓO₂ for a Stacked Gate-all-Around Nanowire Ferroelectric FET With Internal Metal Gate

IEEE Journal of the Electron Devices Society, 2021
This study investigates a device’s ability to boost its on-state current and subthreshold behavior using a ferroelectric field-effect transistor (FeFET) with an ultrathin sub-5-nm Hf1-xZrxO2 (HZO). A conventional field-effect transistor (FET) with
Shen-Yang Lee, Chia-Chin Lee, Yi-Shan Kuo, Shou-Wei Li, Tien-Sheng Chao   +4 more
doaj   +1 more source

Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect Transistors

IEEE Journal of the Electron Devices Society, 2019
Present work demonstrates the vertically double stacked nanosheet (NS) p-channel polycrystalline silicon (poly-Si) junctionless field-effect transistors (JL-FET) with tri-gate, omega-gate, and gate all around (GAA) structure.
Meng-Ju Tsai, Kang-Hui Peng, Chong-Jhe Sun, Siao-Cheng Yan, Chieng-Chung Hsu, Yu-Ru Lin, Yu-Hsien Lin, Yung-Chun Wu   +7 more
doaj   +1 more source

Improvement in Self-Heating Characteristic by Incorporating Hetero-Gate-Dielectric in Gate-All-Around MOSFETs

IEEE Journal of the Electron Devices Society, 2021
For improving self-heating effects (SHEs) in gate-all-around metal-oxide-semiconductor field-effect transistors (GAA MOSFETs), hetero-gate-dielectric (HGD) is utilized. The HGD consists of hafnium dioxide (HfO2) and silicon dioxide (SiO2), which has high
Young Suh Song, Jang Hyun Kim, Garam Kim, Hyun-Min Kim, Sangwan Kim, Byung-Gook Park   +5 more
doaj   +1 more source

NEGF simulations of a junctionless Si gate-all-around nanowire transistor with discrete dopants [PDF]

, 2012
We have carried out 3D Non-Equilibrium Green Function simulations of ajunctionlessgate-all-around n-type silicon nanowiretransistor of 4.2 × 4.2 nm2 cross-section. We model the dopants in a fully atomistic way.
Brown, A., Asenov, A., A. Martinez, Aldegunde, M., M. Aldegunde, A. Asenov, Martinez, A., Antonio Martinez Muniz, A.R. Brown, Roy, S., S. Roy   +10 more
core   +1 more source

Design of GAA Nanosheet Ferroelectric Area Tunneling FET and Its Significance with DC/RF Characteristics Including Linearity Analyses

Nanoscale Research Letters, 2022
This work reports an emerging structure of gate-all-around ferroelectric area tunneling field-effect transistor (FATFET) by considering ferroelectric and a n-epitaxial layer enveloped around the overlapped region of the source and channel to succeed with
Narasimhulu Thoti, Yiming Li
doaj   +1 more source

Performance of Stacked Nanosheets Gate-All-Around and Multi-Gate Thin-Film-Transistors

IEEE Journal of the Electron Devices Society, 2018
This comprehensive study of the horizontally p-type stacked nanosheets inversion mode thinfilm transistor with gate-all-around (SNS-GAATFT) and multi-gate (SNS-TFT) structures.
Yu-Ru Lin, Yi-Yun Yang, Yu-Husien Lin, Erry Dwi Kurniawan, Mu-Shih Yeh, Lun-Chun Chen, Yug-Chun Wu   +6 more
doaj   +1 more source

Numerical Investigations of Nanowire Gate-All-Around Negative Capacitance GaAs/InN Tunnel FET

IEEE Access, 2022
We demonstrated a nanowire gate-all-around (GAA) negative capacitance (NC) tunnel field-effect transistor (TFET) based on the GaAs/InN heterostructure using TCAD simulation.
Abdullah Al Mamun Mazumder, Kamal Hosen, Md. Sherajul Islam, Jeongwon Park   +3 more
doaj   +1 more source

A Nanosized-Metal-Grain Pattern-Dependent Threshold Voltage Model for the Work Function Fluctuation of GAA Si NW MOSFETs

IEEE Access, 2021
To estimate characteristic fluctuation of emerging devices, three-dimensional device simulation has been performed intensively for various random cases; however, it strongly relies on huge computational resources.
Wen-Li Sung, Yiming Li
doaj   +1 more source

A non-destructive channel stress characterization for gate-all-around nanosheet transistors by confocal Raman methodology

National Science Open, 2022
Non-destructive stress characterization is essential for gate-all-around (GAA) nanosheet (NS) transistors technology, while it is a big challenge to be realized on nanometer-sized GAA devices by using traditional Micro-Raman spectroscopy due to its light
Huang Ziqiang, Liu Tao, Yang Jingwen, Sun Xin, Chen Kun, Wang Dawei, Hu Hailong, Xu Min, Wang Chen, Xu Saisheng, Zhang David Wei   +10 more
doaj   +1 more source

Effects of Etching Variations on Ge/Si Channel Formation and Device Performance

Nanoscale Research Letters, 2018
During the formation of Ge fin structures on a silicon-on-insulator (SOI) substrate, we found that the dry etching process must be carefully controlled. Otherwise, it may lead to Ge over-etching or the formation of an undesirable Ge fin profile.
Jiann-Lin Chen, Yiin-Kuen Fuh, Chun-Lin Chu   +2 more
doaj   +1 more source