Results 11 to 20 of about 12,503,659 (299)

A Novel Germanium-Around-Source Gate-All-Around Tunnelling Field-Effect Transistor for Low-Power Applications [PDF]

Micromachines, 2020
This paper presents a germanium-around-source gate-all-around tunnelling field-effect transistor (GAS GAA TFET). The electrical characteristics of the device were studied and compared with those of silicon gate-all-around and germanium-based-source gate ...
Ke Han, Shanglin Long, Zhongliang Deng, Yannan Zhang, Jiawei Li   +4 more
doaj   +3 more sources

Cryogenic Transport Characteristics of P-Type Gate-All-Around Silicon Nanowire MOSFETs [PDF]

Nanomaterials, 2021
A 16-nm-Lg p-type Gate-all-around (GAA) silicon nanowire (Si NW) metal oxide semiconductor field effect transistor (MOSFET) was fabricated based on the mainstream bulk fin field-effect transistor (FinFET) technology.
Jie Gu, Qingzhu Zhang, Zhenhua Wu, Jiaxin Yao, Zhaohao Zhang, Xiaohui Zhu, Guilei Wang, Junjie Li, Yongkui Zhang, Yuwei Cai, Renren Xu, Gaobo Xu, Qiuxia Xu, Huaxiang Yin, Jun Luo, Wenwu Wang, Tianchun Ye   +16 more
doaj   +2 more sources

Vertical Gate-All-Around Device Architecture to Improve the Device Performance for Sub-5-nm Technology [PDF]

Micromachines, 2022
In this work, we propose a vertical gate-all-around device architecture (GAA-FinFET) with the aim of simultaneously improving device performance as well as addressing the short channel effect (SCE).
Changwoo Noh, Changwoo Han, Sang Min Won, Changhwan Shin   +3 more
doaj   +2 more sources

An Overview of Hot Carrier Degradation on Gate-All-Around Nanosheet Transistors [PDF]

Micromachines
Gate-All-Around (GAA) Nanosheet (NS) transistors have been identified as the device architecture for 3 nm and beyond as they provide additional scaling benefits.
Huimei Zhou
doaj   +2 more sources

Comprehensive Study of Stacked Nanosheet-Type Channel Based on Junctionless Gate-All-Around Thin-Film Transistors

IEEE Journal of the Electron Devices Society, 2019
As technology develops, the stacked nanosheet (NS) structure demonstrates promise for use in future technology nodes. This study demonstrated the excellent performance of stacked-NS channels with junctionless gate-all-around thin-film transistors and ...
Yu-Ru Lin, Yu-Hsien Lin, Yi-Yun Yang, Yung-Chun Wu   +3 more
doaj   +2 more sources

Nanodevices Tend to Be Round

Micromachines, 2021
Under several circumstances, a nanowire transistor with a square cross-section behaves as a circular. Taking the Gate-All-Around junctionless transistor as a primary example, we investigate the transition of the conductive region from square to circle ...
Georges Pananakakis, Gérard Ghibaudo, Sorin Cristoloveanu   +2 more
doaj   +1 more source

Sub-10 nm Top Width Nanowire InGaAs Gate-All-Around MOSFETs With Improved Subthreshold Characteristics and Device Reliability

IEEE Journal of the Electron Devices Society, 2022
In this article, sub-10 nm top width nanowire In0.53Ga0.47As gate-all-around (GAA) MOSFETs with improved subthreshold characteristics and reliability are demonstrated.
Hua-Lun Ko, Quang Ho Luc, Ping Huang, Jing-Yuan Wu, Si-Meng Chen, Nhan-Ai Tran, Heng-Tung Hsu, Edward Yi Chang   +7 more
doaj   +1 more source

A Vertically Stacked Nanosheet Gate-All-Around FET for Biosensing Application

IEEE Access, 2021
In this paper, a vertically stacked nanosheet gate-all-around field-effect transistor (GAA-NSFET) as a label-free biosensor has been proposed and investigated.
Cong Li, Feichen Liu, Ru Han, Yiqi Zhuang   +3 more
doaj   +1 more source

A Dual Core Source/Drain GAA FinFET

Tecnología en Marcha, 2023
The emergence of fin-shaped field effect transistors (FinFETs) was governed by the requirement of the VLSI industry to include more functionalities per unit chip area. Enhanced gate control in a FinFET due to a surrounding gate architecture built on the
Prachuryya Subash Das, Deepjyoti Deb, Rupam Goswami, Santanu Sharma, Rajesh Saha, Hirakjyoti Choudhury   +5 more
doaj   +1 more source

Narrow Sub-Fin Technique for Suppressing Parasitic-Channel Effect in Stacked Nanosheet Transistors

IEEE Journal of the Electron Devices Society, 2022
A new approach of narrowing sub-fin with little extra process cost for suppressing parasitic-channel-effect (PCE) on vertically-stacked horizontal gate-all-around (GAA) Si nanosheet field-effect-transistors (NS-FETs) is proposed.
Jie Gu, Qingzhu Zhang, Zhenhua Wu, Yanna Luo, Lei Cao, Yuwei Cai, Jiaxin Yao, Zhaohao Zhang, Gaobo Xu, Huaxiang Yin, Jun Luo, Wenwu Wang   +11 more
doaj   +1 more source