Results 31 to 40 of about 12,503,659 (299)
An Analytical Gate-All-Around MOSFET Model for Circuit Simulation
Advances in Materials Science and Engineering, 2015 A generic charge-based compact model for undoped (lightly doped) quadruple-gate (QG) and cylindrical-gate MOSFETs using Verilog-A is developed. This model is based on the exact solution of Poisson’s equation with scale length.
Kuan-Chou Lin +2 more
doaj +1 more source
Suspended InAsnanowire gate-all-around field-effect transistors
, 2014 Gate-all-around field-effect transistors are realized with thin, single-crystalline, pure-phase InAs nanowires grown by molecular beam epitaxy. At room temperature, the transistors show a desired high on-state current I-on of similar to 10 mu A arid an ...
Shaoyun Huang +18 more
core +1 more source
IEEE Access, 2023 A new vertical transistor structure based on GaN nanowire is designed and optimized using the TCAD-Santaurus tool with an electrothermal model. The studied structure with quasi-1D drift region is adapted to GaN nanowires synthesized with the bottom-up ...
Mohammed Benjelloun +6 more
doaj +1 more source
Accurate modeling of gate capacitance in deep submicron MOSFETs with high-K gate-dielectrics
, 2004 Gate capacitance of metal-oxide-semiconductor devices with ultra-thin high-K gate-dielectric materials is calculated taking into account the penetration of wave functions into the gate-dielectric.
Haque, A., Hakim, M.M.A.
core +1 more source
High-Performance Silicon Nanowire Electronics [PDF]
, 2012 This thesis explores 10-nm wide Si nanowire (SiNW) field-effect transistors (FETs) for logic applications via the fabrication and testing of SiNW-based ring oscillators.
Huang, Ruo-Gu
core +1 more source
Self-aligned silicidation of surround gate vertical MOSFETs for low cost RF applications
, 2010 We report for the first time a CMOS-compatible silicidation technology for surround-gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for silicidation and is successfully
Tan, L. +16 more
core +1 more source
Small Signal Parameter Extraction of III-V Heterojunction Surrounding Gate Tunnel Field Effect Transistor [PDF]
Журнал нано- та електронної фізики, 2017 This work presents simulation study and analysis of nanoscale III-V Heterojunction Gate All Around Tunnel Field Effect Transistor, along with the extraction of small signal parameters of the device.
ManjulaВ Vijh +2 more
doaj +1 more source
The interface states in gate-all-around transistors (GAAFETs)
, 2023 The atomic-level structural detail and the quantum effects are becoming crucial to device performance as the emerging advanced transistors, representatively GAAFETs, are scaling down towards sub-3nm nodes. However, a multiscale simulation framework based on atomistic models and ab initio quantum simulation is still absent.
Liu, Yue-Yang +7 more
openaire +2 more sources
A Study Of Gate-All-Around Transistors By Electron Tomography [PDF]
AIP Conference Proceedings, 2009 Gate‐all‐around (GAA) SiGe nanowire transistor structures have been studied using high angle annular dark field (HAADF) STEM tomography. Sample preparation has been optimized by isolating single devices in needle‐shaped specimens, using annular milling in the focused ion beam (FIB). Using this technique, images can be acquired over a tilt range up to +/
P. D. Cherns +14 more
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Tau acetylation at K331 has limited impact on tau pathology in vivo
FEBS Letters, EarlyView.We mapped tau post‐translational modifications in humanized MAPT knock‐in mice and in amyloid‐bearing double knock‐in mice. Acetylation within the repeat domain, particularly around K331, showed modest increases under amyloid pathology. To test functional relevance, we generated MAPTK331Q knock‐in mice.
Shoko Hashimoto +3 more
wiley +1 more source