Results 51 to 60 of about 85,934 (320)
We investigate transport properties of gate-all-around Si nanowires using non-equilibrium Green's function technique. By taking into account of the ionized impurity scattering we calculate Green's functions self-consistently and examine the effects of ...
D. Ahn +10 more
core +1 more source
Characteristics of gate-all-around silicon nanowire field effect transistors with asymmetric channel width and source/drain doping concentration [PDF]
We performed 3D simulations to demonstrate structural effects in sub-20 nm gate-all-around silicon nanowire field effect transistors having asymmetric channel width along the channel direction.
Bangsaruntip S. +13 more
core +1 more source
A new vertical transistor structure based on GaN nanowire is designed and optimized using the TCAD-Santaurus tool with an electrothermal model. The studied structure with quasi-1D drift region is adapted to GaN nanowires synthesized with the bottom-up ...
Mohammed Benjelloun +6 more
doaj +1 more source
We fabricated for the first time vertically and laterally integrated III-V 4D transistors. III-V gate-all-around (GAA) nanowire MOSFETs with \(3×4\) arrays show high drive current of \(1.35mA/ \mu m\) and high transconductance of \(0.85mS/ \mu m\).
Gordon, Roy Gerald +6 more
core +1 more source
Gate-all-around silicon nanowire FET modeling [PDF]
As a further extension of the multi-gate MOSFET, the gate-all-around (GAA) silicon nanowire FET is the most promising nanostructure design for next generation semiconductor device. Recent research work demonstrates the excellent device performance of GAA silicon nanowire FET, especially the gate controllability and short channel effect immunity.
openaire +2 more sources
Variability Improvement by Interface Passivation and EOT Scaling of InGaAs Nanowire MOSFETs [PDF]
High-performance InGaAs gate-all-around (GAA) nanowire MOSFETs with channel length (\(L_{ch}\)) down to 20 nm are fabricated by integrating a higher-k \(LaAlO_3\)-based gate-stack with an equivalent oxide thickness of 1.2nm. It is found that inserting an
Gordon, Roy Gerald +4 more
core +2 more sources
Small Signal Parameter Extraction of III-V Heterojunction Surrounding Gate Tunnel Field Effect Transistor [PDF]
This work presents simulation study and analysis of nanoscale III-V Heterojunction Gate All Around Tunnel Field Effect Transistor, along with the extraction of small signal parameters of the device.
ManjulaВ Vijh +2 more
doaj +1 more source
Simulation study of vertically stacked lateral Si nanowires transistors for 5 nm CMOS applications [PDF]
In this paper we present a simulation study of vertically stacked lateral nanowires transistors (NWTs), which may have applications at 5nm CMOS technology.
Adamu-Lema, F. +3 more
core +1 more source
Tau acetylation at K331 has limited impact on tau pathology in vivo
We mapped tau post‐translational modifications in humanized MAPT knock‐in mice and in amyloid‐bearing double knock‐in mice. Acetylation within the repeat domain, particularly around K331, showed modest increases under amyloid pathology. To test functional relevance, we generated MAPTK331Q knock‐in mice.
Shoko Hashimoto +3 more
wiley +1 more source
Using ultra-thin parylene films as an organic gate insulator in nanowire field-effect transistors
We report the development of nanowire field-effect transistors featuring an ultra-thin parylene film as a polymer gate insulator. The room temperature, gas-phase deposition of parylene is an attractive alternative to oxide insulators prepared at high ...
Carrad, D.J., +9 more
core +1 more source

