Results 61 to 70 of about 12,503,659 (299)
Additive manufacturing provides precise control over the placement of continuous fibres within polymer matrices, enabling customised mechanical performance in composite components. This article explores processing strategies, mechanical testing, and modelling approaches for additive manufactured continuous fibre‐reinforced composites.
Cherian Thomas, Amir Hosein Sakhaei
wiley +1 more source
Parametric Data Study of High-k Gate with Dielectric Pocket(DP) Gate All Around(GAA) FETs
This paper presents the parameteric data study of the High-k Gate stack with Dielectric Pocket(DP) Gate All Around(GAA) FETs. A High K gate stack and dielectric pockets inside the channel have been used as a performance booster in the device.
PSIT COE, H (via Mendeley Data)
core +1 more source
An Experimental High‐Throughput Approach for the Screening of Hard Magnet Materials
An entire workflow for the high‐throughput characterization and analysis of compositionally graded magnetic films is presented. Characterization protocols, data management tools and data analysis approaches are illustrated with test case Sm(Fe, V)12 based films.
William Rigaut +16 more
wiley +1 more source
An all‐in‐one analog AI accelerator is presented, enabling on‐chip training, weight retention, and long‐term inference acceleration. It leverages a BEOL‐integrated CMO/HfOx ReRAM array with low‐voltage operation (<1.5 V), multi‐bit capability over 32 states, low programming noise (10 nS), and near‐ideal weight transfer.
Donato Francesco Falcone +11 more
wiley +1 more source
Two Dimensional Modeling of III-V Heterojunction Gate All Around Tunnel Field Effect Transistor [PDF]
Tunnel Field Effect Transistor is one of the extensively researched semiconductor devices, which has captured attention over the conventional Metal Oxide Semiconductor Field Effect Transistor.
Manjula Vijh +2 more
doaj +1 more source
50-nm self-aligned and 'standard' T-gate InP pHEMT comparison: the influence of parasitics on performance at the 50-nm node [PDF]
Continued research into the development of III-V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date.
Elgaid, Khaled +11 more
core +1 more source
Edible electronics needs integrated logic circuits for computation and control. This work presents a potentially edible printed chitosan‐gated transistor with a design optimized for integration in circuits. Its implementation in integrated logic gates and circuits operating at low voltage (0.7 V) is demonstrated, as well as the compatibility with an ...
Giulia Coco +8 more
wiley +1 more source
Edge effects characterization in gate-all-around SOI MOSFETs
The well-known edge effect due to conduction in the parasitic edge transistor at low gate voltages takes place when the threshold voltage is lowered at the device edges.
Flandre, Denis +4 more
core +1 more source
Oxygen‐tunnel (OT) indium tin oxide (ITO) vertical channel transistors (VCTs) enable reliable, high‐density gain‐cell memory for monolithic 3D integration. A sandwiched SiN/SiO2/SiN OT stack selectively regulates oxygen transport, suppressing parasitic electrode oxidation while stabilizing channel oxygen vacancies, thereby suppressing carrier injection
Hyeonho Gu +17 more
wiley +1 more source
A swelling‐programmed micropatterned hydrogel guides adherent cells through a controlled transition from cell–matrix anchoring to cadherin‐mediated cell–cell compaction, enabling rapid assembly of high‐viability spheroids with defined size and morphology.
Han Gyeol Nam +8 more
wiley +1 more source

