Results 1 to 10 of about 1,221 (182)

3-Levels Vertically Stacked Si Nanosheet GAA pFETs with Low-Temperature Interface Treatment for Cryogenic Application [PDF]

Nanomaterials
Cryogenic CMOS technology provides a promising approach to surpass the Boltzmann limit and advance Moore’s Law, addressing the increasing demand for high-performance computing. However, at cryogenic temperatures, the subthreshold swing (SS) of the device
Lewen Qian, Tao Liu, Meicheng Liao, Xinlong Guo, Saisheng Xu, Min Xu, David Wei Zhang   +6 more
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Wafer-scale uniform epitaxy of transferable 2D single crystals for gate-all-around nanosheet field effect transistors [PDF]

Nature Communications
Gate-all-around (GAA) nanosheet field-effect transistors (FETs) with two-dimensional (2D) semiconductor channels surrounded by high-κ dielectrics show outstanding performance and hold promise for ultimate miniaturization in the post-Moore era.
Chengyuan Xue, Congwei Tan, Xin Gao, Junchuan Tang, Weiyu Sun, Yuling Yin, Mengdi Wang, Xiaoyin Gao, Hao An, Boyang Fu, Wanqing Liu, Yuteng Wang, Ye Li, Feng Ding, Hailin Peng   +14 more
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Improving the Performance of Arsenene Nanoribbon Gate-All-Around Tunnel Field-Effect Transistors Using H Defects [PDF]

Nanomaterials
We systematically study the transport properties of arsenene nanoribbon tunneling field-effect transistors (TFETs) along the armchair directions using first-principles calculations based on density functional theory combined with the non-equilibrium ...
Shun Song, Lu Qin, Zhi Wang, Juan Lyu, Jian Gong, Shenyuan Yang   +5 more
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Implementation of Gate-All-Around Gate-Engineered Charge Plasma Nanowire FET-Based Common Source Amplifier

Micromachines, 2023
This paper examines the performance of a Gate-Engineered Gate-All-Around Charge Plasma Nanowire Field Effect Transistor (GAA-DMG-GS-CP NW-FET) and the implementation of a common source (CS) amplifier circuit.
Sarabdeep Singh, Leo Raj Solay, Sunny Anand, Naveen Kumar, Ravi Ranjan, Amandeep Singh   +5 more
doaj   +1 more source

Vertical Gate-All-Around Device Architecture to Improve the Device Performance for Sub-5-nm Technology

Micromachines, 2022
In this work, we propose a vertical gate-all-around device architecture (GAA-FinFET) with the aim of simultaneously improving device performance as well as addressing the short channel effect (SCE).
Changwoo Noh, Changwoo Han, Sang Min Won, Changhwan Shin   +3 more
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A Vertically Stacked Nanosheet Gate-All-Around FET for Biosensing Application

IEEE Access, 2021
In this paper, a vertically stacked nanosheet gate-all-around field-effect transistor (GAA-NSFET) as a label-free biosensor has been proposed and investigated.
Cong Li, Feichen Liu, Ru Han, Yiqi Zhuang   +3 more
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Channel geometry-dependent threshold voltage and transconductance degradation in gate-all-around nanosheet junctionless transistors

AIP Advances, 2021
The gate-all-around (GAA) nanosheet (NS) junctionless transistor (JLT) is an attractive candidate for advanced technology nodes in CMOS scaling. Here, the channel width-dependent transconductance (gm) degradation and threshold voltage (Vth) shift of GAA ...
Dae-Young Jeon
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Narrow Sub-Fin Technique for Suppressing Parasitic-Channel Effect in Stacked Nanosheet Transistors

IEEE Journal of the Electron Devices Society, 2022
A new approach of narrowing sub-fin with little extra process cost for suppressing parasitic-channel-effect (PCE) on vertically-stacked horizontal gate-all-around (GAA) Si nanosheet field-effect-transistors (NS-FETs) is proposed.
Jie Gu, Qingzhu Zhang, Zhenhua Wu, Yanna Luo, Lei Cao, Yuwei Cai, Jiaxin Yao, Zhaohao Zhang, Gaobo Xu, Huaxiang Yin, Jun Luo, Wenwu Wang   +11 more
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Power Reduction in Punch-Through Current-Based Electro-Thermal Annealing in Gate-All-Around FETs

Micromachines, 2022
Device guidelines for reducing power with punch-through current annealing in gate-all-around (GAA) FETs were investigated based on three-dimensional (3D) simulations.
Min-Kyeong Kim, Yang-Kyu Choi, Jun-Young Park   +2 more
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A non-destructive channel stress characterization for gate-all-around nanosheet transistors by confocal Raman methodology

National Science Open, 2022
Non-destructive stress characterization is essential for gate-all-around (GAA) nanosheet (NS) transistors technology, while it is a big challenge to be realized on nanometer-sized GAA devices by using traditional Micro-Raman spectroscopy due to its light
Huang Ziqiang, Liu Tao, Yang Jingwen, Sun Xin, Chen Kun, Wang Dawei, Hu Hailong, Xu Min, Wang Chen, Xu Saisheng, Zhang David Wei   +10 more
doaj   +1 more source