Results 11 to 20 of about 1,221 (182)

Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices

Nanomaterials, 2021
In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated.
Qingzhu Zhang, Jie Gu, Renren Xu, Lei Cao, Junjie Li, Zhenhua Wu, Guilei Wang, Jiaxin Yao, Zhaohao Zhang, Jinjuan Xiang, Xiaobin He, Zhenzhen Kong, Hong Yang, Jiajia Tian, Gaobo Xu, Shujuan Mao, Henry H. Radamson, Huaxiang Yin, Jun Luo   +18 more
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Impact of Stress and Dimension on Nanosheet Deformation during Channel Release of Gate-All-Around Device

Micromachines, 2023
In this paper, nanosheet deformation during channel release has been investigated and discussed in Gate-All-Around (GAA) transistors. Structures with different source/drain size and stacked Si nanosheet lengths were designed and fabricated.
Jingwen Yang, Kun Chen, Dawei Wang, Tao Liu, Xin Sun, Qiang Wang, Ziqiang Huang, Zhecheng Pan, Saisheng Xu, Chen Wang, Chunlei Wu, Min Xu, David Wei Zhang   +12 more
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Recent Developments in Negative Capacitance Gate-All-Around Field Effect Transistors: A Review

IEEE Access, 2023
With transistors scaling down to 3 nm node and beyond, short channel effect (SCE) as well as power consumption dissipation present immense challenges for further scaling down of the transistor.
Laixiang Qin, Chunlai Li, Yiqun Wei, Guoqing Hu, Jingbiao Chen, Yi Li, Caixia Du, Zhangwei Xu, Xiumei Wang, Jin He   +9 more
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A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core–Insulator

Micromachines, 2020
Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy ...
Yannan Zhang, Ke Han, and Jiawei Li
doaj   +1 more source

Source/Drain Trimming Process to Improve Gate-All-Around Nanosheet Transistors Switching Performance and Enable More Stacks of Nanosheets

Micromachines, 2022
A new S/D trimming process was proposed to significantly reduce the parasitic RC of gate-all-around (GAA) nanosheet transistors (NS-FETs) while retaining the channel stress from epitaxy S/D stressors at most. With optimized S/D trimming, the 7-stage ring
Kun Chen, Jingwen Yang, Tao Liu, Dawei Wang, Min Xu, Chunlei Wu, Chen Wang, Saisheng Xu, David Wei Zhang, Wenchao Liu   +9 more
doaj   +1 more source

Cryogenic Transport Characteristics of P-Type Gate-All-Around Silicon Nanowire MOSFETs

Nanomaterials, 2021
A 16-nm-Lg p-type Gate-all-around (GAA) silicon nanowire (Si NW) metal oxide semiconductor field effect transistor (MOSFET) was fabricated based on the mainstream bulk fin field-effect transistor (FinFET) technology.
Jie Gu, Qingzhu Zhang, Zhenhua Wu, Jiaxin Yao, Zhaohao Zhang, Xiaohui Zhu, Guilei Wang, Junjie Li, Yongkui Zhang, Yuwei Cai, Renren Xu, Gaobo Xu, Qiuxia Xu, Huaxiang Yin, Jun Luo, Wenwu Wang, Tianchun Ye   +16 more
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FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability

IEEE Journal of the Electron Devices Society, 2018
Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two experimentally based devices, a 25-nm gate length FinFET and a 22-nm GAA NW are
Daniel Nagy, Guillermo Indalecio, Antonio J. Garcia-Loureiro, Muhammad A. Elmessary, Karol Kalna, Natalia Seoane   +5 more
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A Novel Germanium-Around-Source Gate-All-Around Tunnelling Field-Effect Transistor for Low-Power Applications

Micromachines, 2020
This paper presents a germanium-around-source gate-all-around tunnelling field-effect transistor (GAS GAA TFET). The electrical characteristics of the device were studied and compared with those of silicon gate-all-around and germanium-based-source gate ...
Ke Han, Shanglin Long, Zhongliang Deng, Yannan Zhang, Jiawei Li   +4 more
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Analog and RF performance optimization for gate all around tunnel FET using broken-gap material

Scientific Reports, 2022
Many times, the fabricated cylindrical gate-all-around tunnel FET (GAA TFET) has an uneven radius due to several etching and deposition processes involved while fabricating the device, which show notable variations in the performance of the device.
Pankaj Kumar, Kalyan Koley, Bhubon C. Mech, Ashish Maurya, Subindu Kumar   +4 more
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Nanodevices Tend to Be Round

Micromachines, 2021
Under several circumstances, a nanowire transistor with a square cross-section behaves as a circular. Taking the Gate-All-Around junctionless transistor as a primary example, we investigate the transition of the conductive region from square to circle ...
Georges Pananakakis, Gérard Ghibaudo, Sorin Cristoloveanu   +2 more
doaj   +1 more source