Results 41 to 50 of about 11,867 (200)
, 2010 An analytic subthreshold potential model for gate underlap cylindrical gate-all-around (GAA) MOSFETs is presented in this work. The fringing field from the gate to underlap regions is derived by using channel length transformation and conformal mapping ...
Zhang, Lining +4 more
core +1 more source
Total-Ionizing-Dose Response of Highly Scaled Gate-All-Around Si Nanowire CMOS Transistors
, 2021 Gate-all-around (GAA) silicon nanowire (NW) CMOS transistors demonstrate outstanding total-ionizing-dose (TID) tolerance due to the ultrascaled gate dielectric thickness, enhanced electrostatic gate control, and suppression of parasitic leakage current ...
Gorchichko M. +8 more
core +1 more source
Engineering Reports, Volume 8, Issue 5, May 2026.This graphical abstract compares circuit‐based, signal‐processing‐based, and intelligent‐learning‐based approaches for secondary arc‐fault detection, highlighting their key principles and practical advantages. ABSTRACT Reliable detection of free‐air electric arc faults in high‐voltage overhead transmission lines, together with accurate discrimination ...
Mahyar Abasi +2 more
wiley +1 more source
Analytical subthreshold channel potential model of asymmetric gate underlap gate-all-around MOSFET
, 2010 In this paper an analytic subthreshold potential model for undoped cylindrical gate-all-around (GAA) MOSFET with asymmetric gate underlap is developed.
Zhang, Lining +5 more
core +1 more source
Energy Technology, Volume 14, Issue 5, May 2026.A symmetric boost converter combining a Meissner oscillator with a forward stage enables ultralow‐voltage energy harvesting from thermoelectric generators. The prototype cold‐starts at 18 mV and sustains operation down to 6 mV, achieving > 63% efficiency across 20–50 mV inputs.
Uttunga Gopal Shinde +2 more
wiley +1 more source
Electrostatic Analysis of Gate All Around (GAA) Nanowire over FinFET [PDF]
, 2017 : CMOS Technology has been scaled down to 7 nm with FinFET replacing planar MOSFET devices. Due to short channel effects, the FinFET structure was developed to provide better electrostatic control on subthreshold leakage and saturation current over ...
core
Trap Identification in Gate-All-Around Vertically Stacked Si n-channel Nanosheet FETs
, 2023 International audienceIn this article low frequency noise (LFN) spectroscopy in n-type Si-channel gate-all-around (GAA) vertically stacked lateral nanosheet (NS) FETs with different numbers of nanosheets, and gate lengths is applied. From the temperature
Tahiat, Abderrahim +3 more
core +1 more source
Vertical Heterojunction Ge0.92Sn0.08/Ge Gate-All-Around Nanowire pMOSFETs
, 2019 International audienceVertical heterojunction Ge 0.92 Sn 0.08 /Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a top-down approach are reported.
Grap, Thomas +9 more
core +1 more source
, 2012 In this paper, the performance metrics (i.e., read and write margins, operation speed, power consumption) of 6T SRAM cell based on gate-all-around (GAA) Si nanowire transistor (SNWT) at 16nm technology node are investigated, as well as the impacts of ...
Ru Huang +9 more
core +1 more source
Gate-all-around silicon nanowire FET modeling
, 2014 As a further extension of the multi-gate MOSFET, the gate-all-around (GAA) silicon nanowire FET is the most promising nanostructure design for next generation semiconductor device. Recent research work demonstrates the excellent device performance of GAA
Chen, Xiangchen
core +1 more source