Results 21 to 30 of about 1,279 (182)

Nanodevices Tend to Be Round

Micromachines, 2021
Under several circumstances, a nanowire transistor with a square cross-section behaves as a circular. Taking the Gate-All-Around junctionless transistor as a primary example, we investigate the transition of the conductive region from square to circle ...
Georges Pananakakis, Gérard Ghibaudo, Sorin Cristoloveanu   +2 more
doaj   +1 more source

EFFECT OF PROCESS PARAMETER VARIATION ON ft IN CONVENTIONAL AND JUNCTIONLESS GATE-ALL-AROUND DEVICES [PDF]

Journal of Engineering Science and Technology, 2015
In this paper we have studied the effect of process variations on unity gain cut- off frequency (ft) in conventional and junctionless gate-all-around (GAA) transistors using TCAD simulations. Three different geometrical parameters, channel doping, source/
B. LAKSHMI, R. SRINIVASAN
doaj  

Analog and RF performance optimization for gate all around tunnel FET using broken-gap material

Scientific Reports, 2022
Many times, the fabricated cylindrical gate-all-around tunnel FET (GAA TFET) has an uneven radius due to several etching and deposition processes involved while fabricating the device, which show notable variations in the performance of the device.
Pankaj Kumar, Kalyan Koley, Bhubon C. Mech, Ashish Maurya, Subindu Kumar   +4 more
doaj   +1 more source

A Simulation Study of Gate-All-Around Nanowire Transistor With a Core-Substrate

IEEE Access, 2020
In this letter, a novel Core-Substrate Gate-All-Around (CSGAA) nanowire structure has been proposed, investigated and simulated systematically based on 3D numerical simulation. This new structure is characterized by a Core-Substrate directly connected to
Ke Han, Yannan Zhang, Zhongliang Deng
doaj   +1 more source

Junctionless nanosheet gate‐all‐around transistors fabricated on void embedded silicon on insulator substrate

Electronics Letters, 2023
A novel junctionless gate‐all‐around (GAA) transistor with ultrathin nanosheet GAA channel and self‐aligned raised source/drain (RSD) is successfully designed and fabricated on void embedded silicon on insulator (VESOI) substrate through a much simpler ...
Zhiqiang Mu, Hongyang Zhou, Yumeng Yang, Qiang Liu, Xing Wei, Wenjie Yu   +5 more
doaj   +1 more source

Improvement in Self-Heating Characteristic by Incorporating Hetero-Gate-Dielectric in Gate-All-Around MOSFETs

IEEE Journal of the Electron Devices Society, 2021
For improving self-heating effects (SHEs) in gate-all-around metal-oxide-semiconductor field-effect transistors (GAA MOSFETs), hetero-gate-dielectric (HGD) is utilized. The HGD consists of hafnium dioxide (HfO2) and silicon dioxide (SiO2), which has high
Young Suh Song, Jang Hyun Kim, Garam Kim, Hyun-Min Kim, Sangwan Kim, Byung-Gook Park   +5 more
doaj   +1 more source

The Effect of Channel Variation for Long Channel GaAs Junctionless Gate-All-Around Transistor

Journal of Nano- and Electronic Physics, 2022
Починаючи з епохи Мура, для покращення електричних характеристик було введено використання передової архітектури пристроїв з наноматеріалів. У роботі повідомляється про дослідження характеристик довгоканального GaAs JGAA транзистора, включаючи квантово-механічний ефект.
Rasol, M. Faidzal, T., Ainun, H., Fatimah, J., Zaharah, S. Z. A., Mastura, A., Rashidah, A. Riyad, Munawar   +6 more
openaire   +3 more sources

Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect Transistors

IEEE Journal of the Electron Devices Society, 2019
Present work demonstrates the vertically double stacked nanosheet (NS) p-channel polycrystalline silicon (poly-Si) junctionless field-effect transistors (JL-FET) with tri-gate, omega-gate, and gate all around (GAA) structure.
Meng-Ju Tsai, Kang-Hui Peng, Chong-Jhe Sun, Siao-Cheng Yan, Chieng-Chung Hsu, Yu-Ru Lin, Yu-Hsien Lin, Yung-Chun Wu   +7 more
doaj   +1 more source

Complementary Field Effect Transistor (CFET) for the 2-nm Technology Node: A Review From Device to Circuit Perspectives

IEEE Journal of the Electron Devices Society
The relentless advancement of the semiconductor industry continues to be fueled by the pursuit of enhanced transistor performance. As CMOS technology undergoes aggressive scaling to enable higher integration densities in modern integrated circuits (ICs),
J. Ajayan, Vakkalakula Bharath Sreenivasulu, Amit Krishna Dwivedi, Shubham Tayal   +3 more
doaj   +1 more source

Effects of Random Nanosized TiN Grain on Characteristic of Gate-All-Around FinFETs with Ferroelectric HZO Layer

Nanoscale Research Letters, 2022
In this paper, we computationally study electrical characteristics for gate-all-around fin field effect transistors (GAA FinFETs) and negative capacitance GAA FinFETs (NC-GAA FinFETs) for sub-3-nm technological nodes.
Yiming Li, Min-Hui Chuang, Yu-Chin Tsai
doaj   +1 more source