Results 1 to 10 of about 81,201 (155)

A Review of Reliability in Gate-All-Around Nanosheet Devices [PDF]

Micromachines
The gate-all-around (GAA) nanosheet (NS) field-effect-transistor (FET) is poised to replace FinFET in the 3 nm CMOS technology node and beyond, marking the second seminal shift in device architecture across the extensive 60-plus-year history of MOSFET ...
Miaomiao Wang
doaj   +4 more sources

Switching performance assessment of gate-all-around InAs–Si vertical TFET with triple metal gate, a simulation study [PDF]

Discover Nano, 2023
This study presents a gate-all-around InAs–Si vertical tunnel field-effect transistor with a triple metal gate (VTG-TFET). We obtained improved switching characteristics for the proposed design because of the improved electrostatic control on the channel
Dariush Madadi, Saeed Mohammadi
doaj   +2 more sources

4-Levels Vertically Stacked SiGe Channel Nanowires Gate-All-Around Transistor with Novel Channel Releasing and Source and Drain Silicide Process [PDF]

Nanomaterials, 2022
In this paper, the fabrication and electrical performance optimization of a four-levels vertically stacked Si0.7Ge0.3 channel nanowires gate-all-around transistor are explored in detail. First, a high crystalline quality and uniform stacked Si0.7Ge0.3/Si
Xiaohong Cheng, Yongliang Li, Fei Zhao, Anlan Chen, Haoyan Liu, Chun Li, Qingzhu Zhang, Huaxiang Yin, Jun Luo, Wenwu Wang   +9 more
doaj   +2 more sources

Implementation of Gate-All-Around Gate-Engineered Charge Plasma Nanowire FET-Based Common Source Amplifier [PDF]

Micromachines, 2023
This paper examines the performance of a Gate-Engineered Gate-All-Around Charge Plasma Nanowire Field Effect Transistor (GAA-DMG-GS-CP NW-FET) and the implementation of a common source (CS) amplifier circuit.
Sarabdeep Singh, Leo Raj Solay, Sunny Anand, Naveen Kumar, Ravi Ranjan, Amandeep Singh   +5 more
doaj   +2 more sources

Improving the Performance of Arsenene Nanoribbon Gate-All-Around Tunnel Field-Effect Transistors Using H Defects [PDF]

Nanomaterials
We systematically study the transport properties of arsenene nanoribbon tunneling field-effect transistors (TFETs) along the armchair directions using first-principles calculations based on density functional theory combined with the non-equilibrium ...
Shun Song, Lu Qin, Zhi Wang, Juan Lyu, Jian Gong, Shenyuan Yang   +5 more
doaj   +2 more sources

Impact of Stress and Dimension on Nanosheet Deformation during Channel Release of Gate-All-Around Device [PDF]

Micromachines, 2023
In this paper, nanosheet deformation during channel release has been investigated and discussed in Gate-All-Around (GAA) transistors. Structures with different source/drain size and stacked Si nanosheet lengths were designed and fabricated.
Jingwen Yang, Kun Chen, Dawei Wang, Tao Liu, Xin Sun, Qiang Wang, Ziqiang Huang, Zhecheng Pan, Saisheng Xu, Chen Wang, Chunlei Wu, Min Xu, David Wei Zhang   +12 more
doaj   +2 more sources

Stacked Nanosheet Gate‐All‐Around Morphotropic Phase Boundary Field‐Effect Transistors [PDF]

Advanced Science
A material design method is proposed using ferroelectric (FE)–antiferroelectric (AFE) mixed‐phase HfZrO2 (HZO) to achieve performance improvements in morphotropic phase boundary (MPB) field‐effect transistors (MPB‐FETs), such as steep subthreshold swing (
Sihyun Kim, Hyun‐Min Kim, Ki‐Ryun Kwon, Daewoong Kwon   +3 more
doaj   +2 more sources

Quantum transport through a constriction in nanosheet gate-all-around transistors [PDF]

Communications Engineering
In nanoscale transistors, quantum mechanical effects such as tunneling and quantization significantly influence device characteristics. However, large-scale quantum transport simulation remains a challenging field, making it difficult to account for ...
Kyoung Yeon Kim, Hong-Hyun Park, Seonghoon Jin, Uihui Kwon, Woosung Choi, Dae Sin Kim   +5 more
doaj   +2 more sources

Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices [PDF]

Nanomaterials, 2021
In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated.
Qingzhu Zhang, Jie Gu, Renren Xu, Lei Cao, Junjie Li, Zhenhua Wu, Guilei Wang, Jiaxin Yao, Zhaohao Zhang, Jinjuan Xiang, Xiaobin He, Zhenzhen Kong, Hong Yang, Jiajia Tian, Gaobo Xu, Shujuan Mao, Henry H. Radamson, Huaxiang Yin, Jun Luo   +18 more
doaj   +2 more sources

A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core–Insulator [PDF]

Micromachines, 2020
Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy ...
Yannan Zhang, Ke Han, and Jiawei Li
doaj   +2 more sources