Results 21 to 30 of about 85,432 (295)

A Vertically Stacked Nanosheet Gate-All-Around FET for Biosensing Application

IEEE Access, 2021
In this paper, a vertically stacked nanosheet gate-all-around field-effect transistor (GAA-NSFET) as a label-free biosensor has been proposed and investigated.
Cong Li, Feichen Liu, Ru Han, Yiqi Zhuang   +3 more
doaj   +1 more source

A Dual Core Source/Drain GAA FinFET

Tecnología en Marcha, 2023
The emergence of fin-shaped field effect transistors (FinFETs) was governed by the requirement of the VLSI industry to include more functionalities per unit chip area. Enhanced gate control in a FinFET due to a surrounding gate architecture built on the
Prachuryya Subash Das, Deepjyoti Deb, Rupam Goswami, Santanu Sharma, Rajesh Saha, Hirakjyoti Choudhury   +5 more
doaj   +1 more source

Narrow Sub-Fin Technique for Suppressing Parasitic-Channel Effect in Stacked Nanosheet Transistors

IEEE Journal of the Electron Devices Society, 2022
A new approach of narrowing sub-fin with little extra process cost for suppressing parasitic-channel-effect (PCE) on vertically-stacked horizontal gate-all-around (GAA) Si nanosheet field-effect-transistors (NS-FETs) is proposed.
Jie Gu, Qingzhu Zhang, Zhenhua Wu, Yanna Luo, Lei Cao, Yuwei Cai, Jiaxin Yao, Zhaohao Zhang, Gaobo Xu, Huaxiang Yin, Jun Luo, Wenwu Wang   +11 more
doaj   +1 more source

Ultrathin Sub-5-nm Hf₁₋ₓZrₓO₂ for a Stacked Gate-all-Around Nanowire Ferroelectric FET With Internal Metal Gate

IEEE Journal of the Electron Devices Society, 2021
This study investigates a device’s ability to boost its on-state current and subthreshold behavior using a ferroelectric field-effect transistor (FeFET) with an ultrathin sub-5-nm Hf1-xZrxO2 (HZO). A conventional field-effect transistor (FET) with
Shen-Yang Lee, Chia-Chin Lee, Yi-Shan Kuo, Shou-Wei Li, Tien-Sheng Chao   +4 more
doaj   +1 more source

Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect Transistors

IEEE Journal of the Electron Devices Society, 2019
Present work demonstrates the vertically double stacked nanosheet (NS) p-channel polycrystalline silicon (poly-Si) junctionless field-effect transistors (JL-FET) with tri-gate, omega-gate, and gate all around (GAA) structure.
Meng-Ju Tsai, Kang-Hui Peng, Chong-Jhe Sun, Siao-Cheng Yan, Chieng-Chung Hsu, Yu-Ru Lin, Yu-Hsien Lin, Yung-Chun Wu   +7 more
doaj   +1 more source

Improvement in Self-Heating Characteristic by Incorporating Hetero-Gate-Dielectric in Gate-All-Around MOSFETs

IEEE Journal of the Electron Devices Society, 2021
For improving self-heating effects (SHEs) in gate-all-around metal-oxide-semiconductor field-effect transistors (GAA MOSFETs), hetero-gate-dielectric (HGD) is utilized. The HGD consists of hafnium dioxide (HfO2) and silicon dioxide (SiO2), which has high
Young Suh Song, Jang Hyun Kim, Garam Kim, Hyun-Min Kim, Sangwan Kim, Byung-Gook Park   +5 more
doaj   +1 more source

NEGF simulations of a junctionless Si gate-all-around nanowire transistor with discrete dopants [PDF]

, 2012
We have carried out 3D Non-Equilibrium Green Function simulations of ajunctionlessgate-all-around n-type silicon nanowiretransistor of 4.2 × 4.2 nm2 cross-section. We model the dopants in a fully atomistic way.
Brown, A., Asenov, A., A. Martinez, Aldegunde, M., M. Aldegunde, A. Asenov, Martinez, A., Antonio Martinez Muniz, A.R. Brown, Roy, S., S. Roy   +10 more
core   +1 more source

Design of GAA Nanosheet Ferroelectric Area Tunneling FET and Its Significance with DC/RF Characteristics Including Linearity Analyses

Nanoscale Research Letters, 2022
This work reports an emerging structure of gate-all-around ferroelectric area tunneling field-effect transistor (FATFET) by considering ferroelectric and a n-epitaxial layer enveloped around the overlapped region of the source and channel to succeed with
Narasimhulu Thoti, Yiming Li
doaj   +1 more source

Performance of Stacked Nanosheets Gate-All-Around and Multi-Gate Thin-Film-Transistors

IEEE Journal of the Electron Devices Society, 2018
This comprehensive study of the horizontally p-type stacked nanosheets inversion mode thinfilm transistor with gate-all-around (SNS-GAATFT) and multi-gate (SNS-TFT) structures.
Yu-Ru Lin, Yi-Yun Yang, Yu-Husien Lin, Erry Dwi Kurniawan, Mu-Shih Yeh, Lun-Chun Chen, Yug-Chun Wu   +6 more
doaj   +1 more source

Numerical Investigations of Nanowire Gate-All-Around Negative Capacitance GaAs/InN Tunnel FET

IEEE Access, 2022
We demonstrated a nanowire gate-all-around (GAA) negative capacitance (NC) tunnel field-effect transistor (TFET) based on the GaAs/InN heterostructure using TCAD simulation.
Abdullah Al Mamun Mazumder, Kamal Hosen, Md. Sherajul Islam, Jeongwon Park   +3 more
doaj   +1 more source