Results 31 to 40 of about 18,442,309 (293)

Numerical Investigations of Nanowire Gate-All-Around Negative Capacitance GaAs/InN Tunnel FET

IEEE Access, 2022
We demonstrated a nanowire gate-all-around (GAA) negative capacitance (NC) tunnel field-effect transistor (TFET) based on the GaAs/InN heterostructure using TCAD simulation.
Abdullah Al Mamun Mazumder, Kamal Hosen, Md. Sherajul Islam, Jeongwon Park   +3 more
doaj   +1 more source

Achieving short high-quality gate-all-around structures for horizontal nanowire field-effect transistors [PDF]

, 2018
We introduce a fabrication method for gate-all-around nanowire field-effect transistors. Single nanowires were aligned perpendicular to underlying bottom gates using a resist-trench alignment technique.
Seidl, J, Gluschke, J. G., Ullah, AR, Lehmann, S., Seidl, J.,, Carrad, DJ, Fahlvik, S, Burke, AM, Linke, H.,, Micolich, A. P., Burke, A. M.,, Lehmann, S.,, Micolich, A. P.,, Fahlvik, S.,, Ullah, A. R.,, Fahlvik, S., Linke, H, Burke, A. M., Lehmann, S, Ullah, A. R., Carrad, D. J., Linke, H., Lyttleton, R. W., Gluschke, JG ; https://orcid.org/, Micolich, AP ; https://orcid.org/, Seidl, J., Carrad, D. J.,, Gluschke, J. G.,, Lyttleton, Roman, Lyttleton, R. W.,, Lyttleton, RW, Lund University.   +31 more
core   +1 more source

A Nanosized-Metal-Grain Pattern-Dependent Threshold Voltage Model for the Work Function Fluctuation of GAA Si NW MOSFETs

IEEE Access, 2021
To estimate characteristic fluctuation of emerging devices, three-dimensional device simulation has been performed intensively for various random cases; however, it strongly relies on huge computational resources.
Wen-Li Sung, Yiming Li
doaj   +1 more source

A non-destructive channel stress characterization for gate-all-around nanosheet transistors by confocal Raman methodology

National Science Open, 2022
Non-destructive stress characterization is essential for gate-all-around (GAA) nanosheet (NS) transistors technology, while it is a big challenge to be realized on nanometer-sized GAA devices by using traditional Micro-Raman spectroscopy due to its light
Huang Ziqiang, Liu Tao, Yang Jingwen, Sun Xin, Chen Kun, Wang Dawei, Hu Hailong, Xu Min, Wang Chen, Xu Saisheng, Zhang David Wei   +10 more
doaj   +1 more source

Parametric Data Study of High-k Gate with Dielectric Pocket(DP) Gate All Around(GAA) FETs

, 2021
This paper presents the parameteric data study of the High-k Gate stack with Dielectric Pocket(DP) Gate All Around(GAA) FETs. A High K gate stack and dielectric pockets inside the channel have been used as a performance booster in the device.
PSIT COE, H (via Mendeley Data), Dixit, Manish Kumar   +1 more
core   +1 more source

Effects of Etching Variations on Ge/Si Channel Formation and Device Performance

Nanoscale Research Letters, 2018
During the formation of Ge fin structures on a silicon-on-insulator (SOI) substrate, we found that the dry etching process must be carefully controlled. Otherwise, it may lead to Ge over-etching or the formation of an undesirable Ge fin profile.
Jiann-Lin Chen, Yiin-Kuen Fuh, Chun-Lin Chu   +2 more
doaj   +1 more source

An Analytical Gate-All-Around MOSFET Model for Circuit Simulation

Advances in Materials Science and Engineering, 2015
A generic charge-based compact model for undoped (lightly doped) quadruple-gate (QG) and cylindrical-gate MOSFETs using Verilog-A is developed. This model is based on the exact solution of Poisson’s equation with scale length.
Kuan-Chou Lin, Wei-Wen Ding, Meng-Hsueh Chiang   +2 more
doaj   +1 more source

Suspended InAsnanowire gate-all-around field-effect transistors

, 2014
Gate-all-around field-effect transistors are realized with thin, single-crystalline, pure-phase InAs nanowires grown by molecular beam epitaxy. At room temperature, the transistors show a desired high on-state current I-on of similar to 10 mu A arid an ...
Shaoyun Huang, Xu, Hongqi, Zhao, JH, Wang, Jingyun, Qiang Li, Pan, Dong, Jingyun Wang, Zhao, Jianhua, Wang, JY, Li, Qiang, Dong Pan, Xu, HQ, Huang, Shaoyun, Huang, SY, Jianhua Zhao, Pan, D, Li, Q, H. Q. Xu, Xu, Hongqi,, Lund University.   +19 more
core   +1 more source

Optimization of 3D Stacked Nanosheets in 5nm Gate-all-around Transistor Technology

, 2021
An optimization study of silicon gate-all-around (GAA) devices based on technology computer-aided design tools is presented in this paper. GAA technology guidelines and solutions are provided for low power applications in the 5 nm CMOS technology node ...
Gundu, Anil Kumar, Kursun, Volkan, Anil Kumar Gundu, Volkan Kursun   +3 more
core   +1 more source

Design, Simulation and Optimization of an Enhanced Vertical GaN Nanowire Transistor on Silicon Substrate for Power Electronic Applications

IEEE Access, 2023
A new vertical transistor structure based on GaN nanowire is designed and optimized using the TCAD-Santaurus tool with an electrothermal model. The studied structure with quasi-1D drift region is adapted to GaN nanowires synthesized with the bottom-up ...
Mohammed Benjelloun, Zahraa Zaidan, Ali Soltani, Noelle Gogneau, Denis Morris, Jean-Christophe Harmand, Hassan Maher Maher   +6 more
doaj   +1 more source