Results 31 to 40 of about 85,724 (295)

Design of GAA Nanosheet Ferroelectric Area Tunneling FET and Its Significance with DC/RF Characteristics Including Linearity Analyses

Nanoscale Research Letters, 2022
This work reports an emerging structure of gate-all-around ferroelectric area tunneling field-effect transistor (FATFET) by considering ferroelectric and a n-epitaxial layer enveloped around the overlapped region of the source and channel to succeed with
Narasimhulu Thoti, Yiming Li
doaj   +1 more source

Parametric Data Study of High-k Gate with Dielectric Pocket(DP) Gate All Around(GAA) FETs [PDF]

, 2021
This paper presents the parameteric data study of the High-k Gate stack with Dielectric Pocket(DP) Gate All Around(GAA) FETs. A High K gate stack and dielectric pockets inside the channel have been used as a performance booster in the device.
PSIT COE, H (via Mendeley Data)
core   +1 more source

Performance of Stacked Nanosheets Gate-All-Around and Multi-Gate Thin-Film-Transistors

IEEE Journal of the Electron Devices Society, 2018
This comprehensive study of the horizontally p-type stacked nanosheets inversion mode thinfilm transistor with gate-all-around (SNS-GAATFT) and multi-gate (SNS-TFT) structures.
Yu-Ru Lin, Yi-Yun Yang, Yu-Husien Lin, Erry Dwi Kurniawan, Mu-Shih Yeh, Lun-Chun Chen, Yug-Chun Wu   +6 more
doaj   +1 more source

Numerical Investigations of Nanowire Gate-All-Around Negative Capacitance GaAs/InN Tunnel FET

IEEE Access, 2022
We demonstrated a nanowire gate-all-around (GAA) negative capacitance (NC) tunnel field-effect transistor (TFET) based on the GaAs/InN heterostructure using TCAD simulation.
Abdullah Al Mamun Mazumder, Kamal Hosen, Md. Sherajul Islam, Jeongwon Park   +3 more
doaj   +1 more source

A Nanosized-Metal-Grain Pattern-Dependent Threshold Voltage Model for the Work Function Fluctuation of GAA Si NW MOSFETs

IEEE Access, 2021
To estimate characteristic fluctuation of emerging devices, three-dimensional device simulation has been performed intensively for various random cases; however, it strongly relies on huge computational resources.
Wen-Li Sung, Yiming Li
doaj   +1 more source

Achieving short high-quality gate-all-around structures for horizontal nanowire field-effect transistors [PDF]

, 2018
We introduce a fabrication method for gate-all-around nanowire field-effect transistors. Single nanowires were aligned perpendicular to underlying bottom gates using a resist-trench alignment technique.
Seidl, J, Gluschke, J. G., Ullah, AR, Lehmann, S., Seidl, J.,, Carrad, DJ, Fahlvik, S, Burke, AM, Linke, H.,, Micolich, A. P., Burke, A. M.,, Lehmann, S.,, Micolich, A. P.,, Fahlvik, S.,, Ullah, A. R.,, Fahlvik, S., Linke, H, Burke, A. M., Lehmann, S, Ullah, A. R., Carrad, D. J., Linke, H., Lyttleton, R. W., Gluschke, JG ; https://orcid.org/, Micolich, AP ; https://orcid.org/, Seidl, J., Carrad, D. J.,, Gluschke, J. G.,, Lyttleton, Roman, Lyttleton, R. W.,, Lyttleton, RW, Lund University.   +31 more
core   +2 more sources

A non-destructive channel stress characterization for gate-all-around nanosheet transistors by confocal Raman methodology

National Science Open, 2022
Non-destructive stress characterization is essential for gate-all-around (GAA) nanosheet (NS) transistors technology, while it is a big challenge to be realized on nanometer-sized GAA devices by using traditional Micro-Raman spectroscopy due to its light
Huang Ziqiang, Liu Tao, Yang Jingwen, Sun Xin, Chen Kun, Wang Dawei, Hu Hailong, Xu Min, Wang Chen, Xu Saisheng, Zhang David Wei   +10 more
doaj   +1 more source

High-Performance Silicon Nanowire Electronics [PDF]

, 2012
This thesis explores 10-nm wide Si nanowire (SiNW) field-effect transistors (FETs) for logic applications via the fabrication and testing of SiNW-based ring oscillators.
Huang, Ruo-Gu
core   +1 more source

Effects of Etching Variations on Ge/Si Channel Formation and Device Performance

Nanoscale Research Letters, 2018
During the formation of Ge fin structures on a silicon-on-insulator (SOI) substrate, we found that the dry etching process must be carefully controlled. Otherwise, it may lead to Ge over-etching or the formation of an undesirable Ge fin profile.
Jiann-Lin Chen, Yiin-Kuen Fuh, Chun-Lin Chu   +2 more
doaj   +1 more source

Edge effects characterization in gate-all-around SOI MOSFETs [PDF]

, 1998
The well-known edge effect due to conduction in the parasitic edge transistor at low gate voltages takes place when the threshold voltage is lowered at the device edges.
Flandre, Denis, Vandooren, Anne, Cristoloveanu, Sorin, IEEE International SOI Conference 1998, Colinge, Jean-Pierre   +4 more
core   +1 more source