Results 11 to 20 of about 85,432 (295)
A Novel Germanium-Around-Source Gate-All-Around Tunnelling Field-Effect Transistor for Low-Power Applications [PDF]
Micromachines, 2020 This paper presents a germanium-around-source gate-all-around tunnelling field-effect transistor (GAS GAA TFET). The electrical characteristics of the device were studied and compared with those of silicon gate-all-around and germanium-based-source gate ...
Ke Han +4 more
doaj +3 more sources
A comparison of performance between double-gate and gate-all-around nanowire MOSFET
Indonesian Journal of Electrical Engineering and Computer Science, 2019 <span lang="EN-MY">Due to the rapid scaling of </span><span>Complementary Metal-Oxide-Semiconductor</span><span lang="EN-MY"> (CMOS), the structure of the planar MOSFET approaches the scaling limits when the short channel effects (SCEs) become the main problem.
Kosmani, Nor Fareza +2 more
openaire +4 more sources
Cryogenic Transport Characteristics of P-Type Gate-All-Around Silicon Nanowire MOSFETs [PDF]
Nanomaterials, 2021 A 16-nm-Lg p-type Gate-all-around (GAA) silicon nanowire (Si NW) metal oxide semiconductor field effect transistor (MOSFET) was fabricated based on the mainstream bulk fin field-effect transistor (FinFET) technology.
Jie Gu +16 more
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Gate electrostatic controllability enhancement in nanotube gate all around field effect transistor
AIP Advances, 2023 Recently, short channel effects (SCE) and power consumption dissipation problems impose tremendous challenges that need imperative actions to be taken to deal with for field effect transistor to further scale down as semiconductor technology enters into sub-10 nm technology node.
Laixiang Qin +4 more
openaire +4 more sources
Vertical Gate-All-Around Device Architecture to Improve the Device Performance for Sub-5-nm Technology [PDF]
Micromachines, 2022 In this work, we propose a vertical gate-all-around device architecture (GAA-FinFET) with the aim of simultaneously improving device performance as well as addressing the short channel effect (SCE).
Changwoo Noh +3 more
doaj +2 more sources
IEEE Journal of the Electron Devices Society, 2019 As technology develops, the stacked nanosheet (NS) structure demonstrates promise for use in future technology nodes. This study demonstrated the excellent performance of stacked-NS channels with junctionless gate-all-around thin-film transistors and ...
Yu-Ru Lin +3 more
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An Overview of Hot Carrier Degradation on Gate-All-Around Nanosheet Transistors [PDF]
MicromachinesGate-All-Around (GAA) Nanosheet (NS) transistors have been identified as the device architecture for 3 nm and beyond as they provide additional scaling benefits.
Huimei Zhou
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Low Temperature HfO₂ Interface Engineering in Dual-Gate and Gate-All-Around MoS₂ Transistors
IEEE Journal of the Electron Devices SocietyThis paper introduces the deposition of seed layers using a soaking technique to deposit dielectric layers on transition metal dichalcogenides (TMDs). This method addresses the bottleneck caused by the lack of dangling bonds in two-dimensional materials,
Po-Heng Pao +3 more
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Micromachines, 2021 Under several circumstances, a nanowire transistor with a square cross-section behaves as a circular. Taking the Gate-All-Around junctionless transistor as a primary example, we investigate the transition of the conductive region from square to circle ...
Georges Pananakakis +2 more
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IEEE Journal of the Electron Devices Society, 2022 In this article, sub-10 nm top width nanowire In0.53Ga0.47As gate-all-around (GAA) MOSFETs with improved subthreshold characteristics and reliability are demonstrated.
Hua-Lun Ko +7 more
doaj +1 more source