Gate-Induced-Drain-Leakage (GIDL) in CMOS Enhanced by Mechanical Stress [PDF]
IEEE Transactions on Electron Devices, 2022 This work was supported in part by the European Commission through the 7th Framework Program (Collaborative project MORDRED) under Contract ...
Kookjin Lee +7 more
core +4 more sources
A Stepped Gate Oxide Structure for Suppressing Gate-Induced Drain Leakage in Fully Depleted Germanium-on-Insulator Multi-Subchannel Tunneling Field-Effect Transistors [PDF]
MicromachinesTo address the severe gate-induced drain leakage (GIDL) issue in fully depleted germanium-on-insulator (FD-GeOI) multi-subchannel tunneling field-effect transistors (MS TFETs), this paper proposes a stepped gate oxide (SGO) structure.
Rui Chen +6 more
doaj +3 more sources
Origin of the Temperature Dependence of Gate-Induced Drain Leakage-Assisted Erase in Three-Dimensional nand Flash Memories [PDF]
MicromachinesThrough detailed experimental and modeling activities, this paper investigates the origin of the temperature dependence of the Erase operation in 3D nand flash arrays.
David G. Refaldi +4 more
doaj +3 more sources
Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash [PDF]
Micromachines, 2023 The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash.
Tao Yang +4 more
doaj +2 more sources
Insight into over Repair of Hot Carrier Degradation by GIDL Current in Si p-FinFETs Using Ultra-Fast Measurement Technique [PDF]
Nanomaterials, 2023 In this article, an experimental study on the gate-induced drain leakage (GIDL) current repairing worst hot carrier degradation (HCD) in Si p-FinFETs is investigated with the aid of an ultra-fast measurement (UFM) technique (~30 μs).
Hao Chang +13 more
doaj +2 more sources
Engineering the ferroelectric polarization to optimize the GIDL and negative output conductance in negative capacitance FET [PDF]
Scientific ReportsThis paper presents the optimization of the gate induced drain leakage (GIDL) and negative output conductance (NOC) effect in ferroelectric negative capacitance (NC) FET by engineering the polarization of ferroelectric. The improvement in NOC and GIDL is
Vijay Sai Thota +2 more
doaj +2 more sources
Optimization of Gate-All-Around Device to Achieve High Performance and Low Power with Low Substrate Leakage [PDF]
Nanomaterials, 2022 In this study on multi-nanosheet field-effect transistor (mNS-FET)—one of the gate-all-around FETs (GAAFET) in the 3 nm technology node dimension—3D TCAD (technology computer-aided design) was used to attain optimally reduced substrate leakage from ...
Changhyun Yoo +4 more
doaj +2 more sources
Gate-induced drain leakage (GIDL) in MFMIS and MFIS negative capacitance FinFETs
Current Applied Physics, 2020 Abstract The gate induced drain leakage (GIDL) effect in negative capacitance (NC) FinFET is investigated. A Landau–Ginzburg–Devonshire equation (which considers the polarization gradient in ferroelectric material) is used to estimate the characteristics of the NC FinFET.
Jinhong Min, Gihun Choe, Changhwan Shin
openaire +2 more sources
Scaling, Leakage Current Suppression, and Simulation of Carbon Nanotube Field-Effect Transistors [PDF]
NanomaterialsCarbon nanotube field-effect transistors (CNTFETs) are becoming a strong competitor for the next generation of high-performance, energy-efficient integrated circuits due to their near-ballistic carrier transport characteristics and excellent suppression ...
Weixu Gong +7 more
doaj +2 more sources
A Novel Channel Preparation Scheme to Optimize Program Disturbance in Three-Dimensional NAND Flash Memory [PDF]
MicromachinesThe program disturbance characteristics of three-dimensional (3D) vertical NAND flash cell array architecture pose a critical reliability challenge due to the lower unselected word line (WL) pass bias (Vpass) window. In other words, the key contradiction
Kaikai You +3 more
doaj +2 more sources