Results 11 to 20 of about 124 (100)

A Novel Channel Preparation Scheme to Optimize Program Disturbance in Three-Dimensional NAND Flash Memory [PDF]

Micromachines
The program disturbance characteristics of three-dimensional (3D) vertical NAND flash cell array architecture pose a critical reliability challenge due to the lower unselected word line (WL) pass bias (Vpass) window. In other words, the key contradiction
Kaikai You, Lei Jin, Jianquan Jia, Zongliang Huo   +3 more
doaj   +2 more sources

Concealable physical unclonable functions using vertical NAND flash memory [PDF]

Nature Communications
Physical Unclonable Functions (PUFs) can address the demand for enhanced hardware security. Vertical NAND (V-NAND) flash memory is the most commercialized non-volatile memory.
Sung-Ho Park, Ryun-Han Koo, Yeongheon Yang, Jiseong Im, Jonghyun Ko, Jong-Ho Lee   +5 more
doaj   +2 more sources

Improving the Gate-Induced Drain Leakage and On-State Current of Fin-Like Thin Film Transistors with a Wide Drain

Applied Sciences, 2018
Polycrystalline silicon (poly-Si) thin film transistors (TFT) with a tri-gate fin-like structure and wide drain were designed and simulated to improve gate-induced drain leakage (GIDL), ON-state current, and breakdown voltage.
Hsin-Hui Hu, Yan-Wei Zeng, Kun-Ming Chen
doaj   +3 more sources

Efficient Erase Operation by GIDL Current for 3D Structure FeFETs With Gate Stack Engineering and Compact Long-Term Retention Model

IEEE Journal of the Electron Devices Society, 2022
We have fabricated junctionless N-type silicon-on-insulator (SOI) ferroelectric-HfO2 field effect transistors (FeFETs) with overlap and underlap structures between gate and drain/source regions to investigate the role of gate-induced-drain-leakage (GIDL)
Fei Mo, Jiawen Xiang, Xiaoran Mei, Yoshiki Sawabe, Takuya Saraya, Toshiro Hiramoto, Chun-Jung Su, Vita Pi-Ho Hu, Masaharu Kobayashi   +8 more
doaj   +1 more source

Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield

Memories - Materials, Devices, Circuits and Systems, 2023
TCAD simulation using Silvaco software has shown that the 3G_DFM, which has SG1 (Select Gate 1), PL (Plate Line Gate), and SG2 (Select Gate 2) between SL (Source Line) and BL (Bit Line), has a long retention time of 100ms at 85 °C, and a robust ...
Koji Sakui, Yisuo Li, Masakazu Kakumu, Kenichi Kanazawa, Iwao Kunishima, Yoshihisa Iwata, Nozomu Harada   +6 more
doaj   +1 more source

Narrow Sub-Fin Technique for Suppressing Parasitic-Channel Effect in Stacked Nanosheet Transistors

IEEE Journal of the Electron Devices Society, 2022
A new approach of narrowing sub-fin with little extra process cost for suppressing parasitic-channel-effect (PCE) on vertically-stacked horizontal gate-all-around (GAA) Si nanosheet field-effect-transistors (NS-FETs) is proposed.
Jie Gu, Qingzhu Zhang, Zhenhua Wu, Yanna Luo, Lei Cao, Yuwei Cai, Jiaxin Yao, Zhaohao Zhang, Gaobo Xu, Huaxiang Yin, Jun Luo, Wenwu Wang   +11 more
doaj   +1 more source

Simulation Acceleration of Bit Error Rate Prediction and Yield Optimization of 3D V-NAND Flash Memory

IEEE Access, 2023
When designing 3D V-NAND technologies with a gate induced drain leakage (GIDL) assisted erase scheme, many experiments must be conducted to determine the optimal GIDL design targets to achieve fast erase performance and secure yield characteristics ...
Yohan Kim, Soyoung Kim
doaj   +1 more source

Comprehensive Analysis of Gate-Induced Drain Leakage in Emerging FET Architectures: Nanotube FETs Versus Nanowire FETs

IEEE Access, 2017
In this paper, we have performed a comprehensive analysis of the gate-induced drain leakage (GIDL) in emerging nanotube (NT) and nanowire (NW) FET architectures.
Shubham Sahay, Mamidala Jagadesh Kumar
doaj   +1 more source

S-TAT Leakage Current in Partial Isolation Type Saddle-FinFET (Pi-FinFET)s

IEEE Access, 2021
In this paper, we compare conventional saddle type FinFETs to partial isolation type saddle FinFETs (Pi-FinFETs) using 3D TCAD simulations to examine the effect of single charge traps for proper prediction of leakage current.
Jin Hyo Park, Geon Kim, Dong Yeong Kim, Su Yeon Kim, Sunyong Yoo, Myoung Jin Lee   +5 more
doaj   +1 more source

Extensionless UTBB FDSOI Devices in Enhanced Dynamic Threshold Mode under Low Power Point of View

Journal of Low Power Electronics and Applications, 2015
This work presents an analysis about the influence of the gate and source/drain underlap length (LUL) on UTBB FDSOI (UltraThin-Body-and-Buried-oxide Fully-Depleted-Silicon-On-Insulator) devices operating in conventional (VB = 0 V), dynamic threshold (DT,
Katia Regina Akemi Sasaki, Marc Aoulaiche, Eddy Simoen, Cor Claeys, Joao Antonio Martino   +4 more
doaj   +1 more source