Results 21 to 30 of about 301 (157)

Model-Inversion-Resistant Physical Unclonable Neural Network Using Vertical NAND Flash Memory. [PDF]

Adv Sci (Weinh)
Schematic and key features of the proposed forward‐forward physical unclonable neural network (FF‐PUNN), incorporating a concealable physical unclonable function (PUF) layer and forward‐forward (FF) learning. ABSTRACT The growing use of neural networks in privacy‐sensitive applications necessitates architectures that inherently protect both data and ...
Park SH, Koo RH, Ko J, Im J, Yang Y, Oh M, Shin D, Jung G, Lee JH.   +8 more
europepmc   +2 more sources

Self-Curable Synaptic Ferroelectric FET Arrays for Neuromorphic Convolutional Neural Network. [PDF]

Adv Sci (Weinh), 2023
The primary challenge that ferroelectric field‐effect transistors face is their vulnerability to the repeated program/erase cycle. To solve this issue, an efficient self‐curing method is presented. The proposed method successfully recovers synaptic fatigue damage, enhancing learning accuracy in the convolutional neural network.
Shin W, Im J, Koo RH, Kim J, Kwon KR, Kwon D, Kim JJ, Lee JH, Kwon D.   +8 more
europepmc   +2 more sources

Stacked Nanosheet Gate-All-Around Morphotropic Phase Boundary Field-Effect Transistors. [PDF]

Adv Sci (Weinh)
This study proposes a material design using ferroelectric‐antiferroelectric mixed‐phase HZO to achieve steep subthreshold swing and non‐hysteretic on‐current enhancement in morphotropic phase boundary field‐effect transistors (MPB‐FETs). For the first time, two‐stacked nanosheet GAA MPB‐FETs with optimized HZO are demonstrated, validating superior ...
Kim S, Kim HM, Kwon KR, Kwon D.
europepmc   +2 more sources

Advancing the Frontiers of HfO₂-Based Ferroelectric Memories: Innovative Concepts from Materials to Applications. [PDF]

Adv Mater
HfO2‐based ferroelectric materials are promising for next‐generation memory technologies by providing outstanding performance aligning with data‐centric computing needs. This review details recent advancements in materials, devices, and integration for HfO2‐based memories, with the goal of identifying both the technological opportunities and remaining ...
Zhou Z, Li L, Feng Y, Wang X, Zheng Z, Jiao L, Zheng H, Shi Y, Ang KW, Gong X.   +9 more
europepmc   +2 more sources

Emerging reconfigurable electronic devices based on two‐dimensional materials: A review

InfoMat, Volume 4, Issue 10, October 2022., 2022
An intense survey of novel reconfigurable devices based on 2D materials is presented with a focus on reconfigurable transistors that offer run‐time control of charge carriers, threshold voltage, and subthreshold swing, and reconfigurable heterostructures manifested as multiple device configurations in one device. The working principles of these devices
Wenwen Fei, Jens Trommer, Max Christian Lemme, Thomas Mikolajick, André Heinzig   +4 more
wiley   +1 more source

Mathematical Modeling and Performance Evaluation of 3D Ferroelectric Negative Capacitance FinFET

Modelling and Simulation in Engineering, Volume 2022, Issue 1, 2022., 2022
Ferroelectric negative capacitance materials have now been proposed for lowering electronics energy dissipation beyond basic limitations. In this paper, we presented the analysis on the performance of negative capacitance (NC) FinFET in comparison with conventional gate dielectrics by using a separation of variables approach, which is an optimal quasi ...
Sayem Ul Alam, Rukon Uddin, Md. Jahangir Alam, Ahamed Raihan, Sheikh S. Mahtab, Subrata Bhowmik, Fahad Al Basir   +6 more
wiley   +1 more source

Review of ferroelectric field‐effect transistors for three‐dimensional storage applications

Nano Select, Volume 2, Issue 6, Page 1187-1207, June 2021., 2021
The ideal hysteresis of the ferroelectric thin film for ferroelectric field effect transistor‐based 3‐dimensional storage devices. The navy‐colored solid curve represents the typical displacement field (Dfer) versus voltage (Vfer) hysteresis. The two vertical arrows indicate that only a small portion of the remanent polarization (Pr) is required for ...
Hyeon Woo Park, Jae‐Gil Lee, Cheol Seong Hwang   +2 more
wiley   +1 more source

Thermal synergies in 50 nanometer CMOS and below

IET Circuits, Devices &Systems, Volume 15, Issue 2, Page 183-196, March 2021., 2021
Abstract An analysis of the metal oxide semiconductor field effect transistor (MOSFET) in strong inversion indicates two bias regions, in each of its triode and saturation conditions, whose distinct properties are elaborated and shown to lead to simple, systematic, design procedures for achieving low temperature coefficient (TC) voltages (<±100 ppm/°C)
F.S. Shoucair
wiley   +1 more source

A Novel Charge Pumping Technique with Gate-Induced Drain Leakage Current

, 2023
A charge pumping (CP) technique with gate-induced drain leakage (GIDL) current is proposed to extract interface trap density ( ${N}_{\text {it}}{)}$ in GAA MOSFETs.
Lee, Geon-Beom, Geon-Beom Lee, Kim, Jeong-Yeon, Jeong-Yeon Kim, Choi, Yang-Kyu, Yang-Kyu Choi   +5 more
core   +1 more source

Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study

IEEE Access, 2020
The leakage mechanisms of inefficient volume depletion and lateral band to band tunneling (L-BTBT) restrict the scaling of SOI-junctionless (JL) FETs. Therefore, in this article, we investigate the scalability of the SOI-JLFETs by incorporating a ground ...
Aakash Kumar Jain, Mamidala Jagadesh Kumar   +1 more
doaj   +1 more source