Results 1 to 10 of about 142 (114)

Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash. [PDF]

Micromachines (Basel), 2023
The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash.
Yang T, Zhang B, Wang Q, Jin L, Xia Z.
europepmc   +2 more sources

Insight into over Repair of Hot Carrier Degradation by GIDL Current in Si p-FinFETs Using Ultra-Fast Measurement Technique. [PDF]

Nanomaterials (Basel), 2023
In this article, an experimental study on the gate-induced drain leakage (GIDL) current repairing worst hot carrier degradation (HCD) in Si p-FinFETs is investigated with the aid of an ultra-fast measurement (UFM) technique (~30 μs).
Chang H, Wang G, Yang H, Liu Q, Zhou L, Ji Z, Yu R, Wu Z, Yin H, Du A, Li J, Luo J, Zhao C, Wang W.   +13 more
europepmc   +2 more sources

Optimization of Gate-All-Around Device to Achieve High Performance and Low Power with Low Substrate Leakage. [PDF]

Nanomaterials (Basel), 2022
In this study on multi-nanosheet field-effect transistor (mNS-FET)—one of the gate-all-around FETs (GAAFET) in the 3 nm technology node dimension—3D TCAD (technology computer-aided design) was used to attain optimally reduced substrate leakage from ...
Yoo C, Chang J, Park S, Kim H, Jeon J.
europepmc   +2 more sources

Incremental Pulse-Width Erase (IPWE) Scheme for Fast and Variation-Tolerant GIDL Erase of 3D NAND Flash. [PDF]

Micromachines (Basel)
In this work, we propose an incremental pulse-width erase (IPWE) scheme for fast and variation-tolerant gate-induced drain leakage (GIDL) erase of 3D NAND flash.
Park Y, Shim W.
europepmc   +2 more sources

A Stepped Gate Oxide Structure for Suppressing Gate-Induced Drain Leakage in Fully Depleted Germanium-on-Insulator Multi-Subchannel Tunneling Field-Effect Transistors. [PDF]

Micromachines (Basel)
To address the severe gate-induced drain leakage (GIDL) issue in fully depleted germanium-on-insulator (FD-GeOI) multi-subchannel tunneling field-effect transistors (MS TFETs), this paper proposes a stepped gate oxide (SGO) structure.
Chen R, Wang L, Han R, Liao K, Shi X, Zhang P, Hu H.   +6 more
europepmc   +2 more sources

Role of mechanical stress on the electrothermal and OFF state current in scaled FinFET devices. [PDF]

Sci Rep
The electrothermal characteristics and leakage current of a tall FinFET device were investigated using the hydrodynamic transport model coupled with a quantum-corrected diffusive transport mechanism-based TCAD simulation.
Shubham, Pandey RK.
europepmc   +2 more sources

Scaling, Leakage Current Suppression, and Simulation of Carbon Nanotube Field-Effect Transistors. [PDF]

Nanomaterials (Basel)
Carbon nanotube field-effect transistors (CNTFETs) are becoming a strong competitor for the next generation of high-performance, energy-efficient integrated circuits due to their near-ballistic carrier transport characteristics and excellent suppression ...
Gong W, Cai Z, Geng S, Gan Z, Li J, Qiang T, Jiang Y, Cai M.   +7 more
europepmc   +2 more sources

Suppressing Gate-Induced Drain Leakage with an Asymmetric Gate Design in HiPco CNT FETs. [PDF]

Nanomaterials (Basel)
Carbon nanotube field-effect transistors (CNT FETs) hold great promise for extending Moore’s Law, yet their performance is critically limited by excessive off-state leakage, caused by band-to-band tunneling (BTBT) in narrow bandgap CNT channels.
Ma H, Gu S, Zhai M, Liu H.
europepmc   +2 more sources

Engineering the ferroelectric polarization to optimize the GIDL and negative output conductance in negative capacitance FET. [PDF]

Sci Rep
This paper presents the optimization of the gate induced drain leakage (GIDL) and negative output conductance (NOC) effect in ferroelectric negative capacitance (NC) FET by engineering the polarization of ferroelectric. The improvement in NOC and GIDL is
Thota VS, Moparthi S, Ghosh K.
europepmc   +2 more sources

Origin of the Temperature Dependence of Gate-Induced Drain Leakage-Assisted Erase in Three-Dimensional nand Flash Memories. [PDF]

Micromachines (Basel)
Through detailed experimental and modeling activities, this paper investigates the origin of the temperature dependence of the Erase operation in 3D nand flash arrays.
Refaldi DG, Malavena G, Chiavarone L, Spinelli AS, Monzio Compagnoni C.   +4 more
europepmc   +2 more sources