Results 21 to 30 of about 311 (157)
Emerging reconfigurable electronic devices based on two‐dimensional materials: A review
InfoMat, Volume 4, Issue 10, October 2022., 2022 An intense survey of novel reconfigurable devices based on 2D materials is presented with a focus on reconfigurable transistors that offer run‐time control of charge carriers, threshold voltage, and subthreshold swing, and reconfigurable heterostructures manifested as multiple device configurations in one device. The working principles of these devices
Wenwen Fei +4 more
wiley +1 more source
Mathematical Modeling and Performance Evaluation of 3D Ferroelectric Negative Capacitance FinFET
Modelling and Simulation in Engineering, Volume 2022, Issue 1, 2022., 2022 Ferroelectric negative capacitance materials have now been proposed for lowering electronics energy dissipation beyond basic limitations. In this paper, we presented the analysis on the performance of negative capacitance (NC) FinFET in comparison with conventional gate dielectrics by using a separation of variables approach, which is an optimal quasi ...
Sayem Ul Alam +6 more
wiley +1 more source
Review of ferroelectric field‐effect transistors for three‐dimensional storage applications
Nano Select, Volume 2, Issue 6, Page 1187-1207, June 2021., 2021 The ideal hysteresis of the ferroelectric thin film for ferroelectric field effect transistor‐based 3‐dimensional storage devices. The navy‐colored solid curve represents the typical displacement field (Dfer) versus voltage (Vfer) hysteresis. The two vertical arrows indicate that only a small portion of the remanent polarization (Pr) is required for ...
Hyeon Woo Park +2 more
wiley +1 more source
Thermal synergies in 50 nanometer CMOS and below
IET Circuits, Devices &Systems, Volume 15, Issue 2, Page 183-196, March 2021., 2021 Abstract An analysis of the metal oxide semiconductor field effect transistor (MOSFET) in strong inversion indicates two bias regions, in each of its triode and saturation conditions, whose distinct properties are elaborated and shown to lead to simple, systematic, design procedures for achieving low temperature coefficient (TC) voltages (<±100 ppm/°C)
F.S. Shoucair
wiley +1 more source
IEEE Access, 2023 When designing 3D V-NAND technologies with a gate induced drain leakage (GIDL) assisted erase scheme, many experiments must be conducted to determine the optimal GIDL design targets to achieve fast erase performance and secure yield characteristics ...
Yohan Kim, Soyoung Kim
doaj +1 more source
IEEE Access, 2017 In this paper, we have performed a comprehensive analysis of the gate-induced drain leakage (GIDL) in emerging nanotube (NT) and nanowire (NW) FET architectures.
Shubham Sahay, Mamidala Jagadesh Kumar
doaj +1 more source
S-TAT Leakage Current in Partial Isolation Type Saddle-FinFET (Pi-FinFET)s
IEEE Access, 2021 In this paper, we compare conventional saddle type FinFETs to partial isolation type saddle FinFETs (Pi-FinFETs) using 3D TCAD simulations to examine the effect of single charge traps for proper prediction of leakage current.
Jin Hyo Park +5 more
doaj +1 more source
A Novel Charge Pumping Technique with Gate-Induced Drain Leakage Current
, 2023 A charge pumping (CP) technique with gate-induced drain leakage (GIDL) current is proposed to extract interface trap density ( ${N}_{\text {it}}{)}$ in GAA MOSFETs.
Lee, Geon-Beom +5 more
core +1 more source
Extensionless UTBB FDSOI Devices in Enhanced Dynamic Threshold Mode under Low Power Point of View
Journal of Low Power Electronics and Applications, 2015 This work presents an analysis about the influence of the gate and source/drain underlap length (LUL) on UTBB FDSOI (UltraThin-Body-and-Buried-oxide Fully-Depleted-Silicon-On-Insulator) devices operating in conventional (VB = 0 V), dynamic threshold (DT,
Katia Regina Akemi Sasaki +4 more
doaj +1 more source
Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study
IEEE Access, 2020 The leakage mechanisms of inefficient volume depletion and lateral band to band tunneling (L-BTBT) restrict the scaling of SOI-junctionless (JL) FETs. Therefore, in this article, we investigate the scalability of the SOI-JLFETs by incorporating a ground ...
Aakash Kumar Jain +1 more
doaj +1 more source