Results 1 to 10 of about 445 (155)

High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

open access: yesIEEE Journal of the Electron Devices Society, 2023
In this work, an experimental evaluation of Gate-Induce Drain Leakage (GIDL) current is presented for nanowire and nanosheet-based SOI transistors. The effects of fin width and temperature increase are studied. Obtained results indicate that the increase
Michelly De Souza   +2 more
exaly   +5 more sources

Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash

open access: yesMicromachines, 2023
The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash.
Tao Yang, Bao Zhang, Zhiliang Xia
exaly   +4 more sources

Insight into over Repair of Hot Carrier Degradation by GIDL Current in Si p-FinFETs Using Ultra-Fast Measurement Technique

open access: yesNanomaterials, 2023
In this article, an experimental study on the gate-induced drain leakage (GIDL) current repairing worst hot carrier degradation (HCD) in Si p-FinFETs is investigated with the aid of an ultra-fast measurement (UFM) technique (~30 μs).
Hao Chang, Longda Zhou, Zhenhua Wu
exaly   +4 more sources

Improving the Gate-Induced Drain Leakage and On-State Current of Fin-Like Thin Film Transistors with a Wide Drain

open access: yesApplied Sciences, 2018
Polycrystalline silicon (poly-Si) thin film transistors (TFT) with a tri-gate fin-like structure and wide drain were designed and simulated to improve gate-induced drain leakage (GIDL), ON-state current, and breakdown voltage.
Hsin-Hui Hu, Yan-Wei Zeng, Kun-Ming Chen
doaj   +2 more sources

Engineering the ferroelectric polarization to optimize the GIDL and negative output conductance in negative capacitance FET

open access: yesScientific Reports
This paper presents the optimization of the gate induced drain leakage (GIDL) and negative output conductance (NOC) effect in ferroelectric negative capacitance (NC) FET by engineering the polarization of ferroelectric. The improvement in NOC and GIDL is
Vijay Sai Thota   +2 more
doaj   +3 more sources

Simulation Acceleration of Bit Error Rate Prediction and Yield Optimization of 3D V-NAND Flash Memory

open access: yesIEEE Access, 2023
When designing 3D V-NAND technologies with a gate induced drain leakage (GIDL) assisted erase scheme, many experiments must be conducted to determine the optimal GIDL design targets to achieve fast erase performance and secure yield characteristics ...
Yohan Kim, Soyoung Kim
doaj   +1 more source

Efficient Erase Operation by GIDL Current for 3D Structure FeFETs With Gate Stack Engineering and Compact Long-Term Retention Model

open access: yesIEEE Journal of the Electron Devices Society, 2022
We have fabricated junctionless N-type silicon-on-insulator (SOI) ferroelectric-HfO2 field effect transistors (FeFETs) with overlap and underlap structures between gate and drain/source regions to investigate the role of gate-induced-drain-leakage (GIDL)
Fei Mo   +8 more
doaj   +1 more source

Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield

open access: yesMemories - Materials, Devices, Circuits and Systems, 2023
TCAD simulation using Silvaco software has shown that the 3G_DFM, which has SG1 (Select Gate 1), PL (Plate Line Gate), and SG2 (Select Gate 2) between SL (Source Line) and BL (Bit Line), has a long retention time of 100ms at 85 °C, and a robust ...
Koji Sakui   +6 more
doaj   +1 more source

ROLE OF PROBIOTICS 0N HEMATOLOGICAL AND IMMUNOLOGICAL PARAMETERS IN GROWEING RABBITS [PDF]

open access: yesJournal of Animal and Poultry Production, 2006
The purpose of the present study was to determine if probiotic (Protexin) supplementation to drinking water at different levels (1.0, 2.5 and 5.09 {Litter of drinking water) would have a beneficial effect on immunological and hematological parameters ...
A. Sedki   +3 more
doaj   +1 more source

Narrow Sub-Fin Technique for Suppressing Parasitic-Channel Effect in Stacked Nanosheet Transistors

open access: yesIEEE Journal of the Electron Devices Society, 2022
A new approach of narrowing sub-fin with little extra process cost for suppressing parasitic-channel-effect (PCE) on vertically-stacked horizontal gate-all-around (GAA) Si nanosheet field-effect-transistors (NS-FETs) is proposed.
Jie Gu   +11 more
doaj   +1 more source

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