Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash [PDF]
Micromachines, 2023 The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash.
Tao Yang
exaly +4 more sources
Engineering the ferroelectric polarization to optimize the GIDL and negative output conductance in negative capacitance FET [PDF]
Scientific ReportsThis paper presents the optimization of the gate induced drain leakage (GIDL) and negative output conductance (NOC) effect in ferroelectric negative capacitance (NC) FET by engineering the polarization of ferroelectric. The improvement in NOC and GIDL is
Vijay Sai Thota +2 more
doaj +4 more sources
High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs
IEEE Journal of the Electron Devices Society, 2023 In this work, an experimental evaluation of Gate-Induce Drain Leakage (GIDL) current is presented for nanowire and nanosheet-based SOI transistors. The effects of fin width and temperature increase are studied. Obtained results indicate that the increase
Michelly De Souza +2 more
exaly +4 more sources
Insight into over Repair of Hot Carrier Degradation by GIDL Current in Si p-FinFETs Using Ultra-Fast Measurement Technique [PDF]
Nanomaterials, 2023 In this article, an experimental study on the gate-induced drain leakage (GIDL) current repairing worst hot carrier degradation (HCD) in Si p-FinFETs is investigated with the aid of an ultra-fast measurement (UFM) technique (~30 μs).
Hao Chang +13 more
doaj +2 more sources
Incremental Pulse-Width Erase (IPWE) Scheme for Fast and Variation-Tolerant GIDL Erase of 3D NAND Flash [PDF]
MicromachinesIn this work, we propose an incremental pulse-width erase (IPWE) scheme for fast and variation-tolerant gate-induced drain leakage (GIDL) erase of 3D NAND flash.
Youngjun Park, Wonbo Shim
doaj +2 more sources
Role of mechanical stress on the electrothermal and OFF state current in scaled FinFET devices [PDF]
Scientific ReportsThe electrothermal characteristics and leakage current of a tall FinFET device were investigated using the hydrodynamic transport model coupled with a quantum-corrected diffusive transport mechanism-based TCAD simulation.
Shubham, Rajan Kumar Pandey
doaj +2 more sources
A Stepped Gate Oxide Structure for Suppressing Gate-Induced Drain Leakage in Fully Depleted Germanium-on-Insulator Multi-Subchannel Tunneling Field-Effect Transistors [PDF]
MicromachinesTo address the severe gate-induced drain leakage (GIDL) issue in fully depleted germanium-on-insulator (FD-GeOI) multi-subchannel tunneling field-effect transistors (MS TFETs), this paper proposes a stepped gate oxide (SGO) structure.
Rui Chen +6 more
doaj +2 more sources
Origin of the Temperature Dependence of Gate-Induced Drain Leakage-Assisted Erase in Three-Dimensional nand Flash Memories [PDF]
MicromachinesThrough detailed experimental and modeling activities, this paper investigates the origin of the temperature dependence of the Erase operation in 3D nand flash arrays.
David G. Refaldi +4 more
doaj +2 more sources
A Novel Channel Preparation Scheme to Optimize Program Disturbance in Three-Dimensional NAND Flash Memory [PDF]
MicromachinesThe program disturbance characteristics of three-dimensional (3D) vertical NAND flash cell array architecture pose a critical reliability challenge due to the lower unselected word line (WL) pass bias (Vpass) window. In other words, the key contradiction
Kaikai You +3 more
doaj +2 more sources
Concealable physical unclonable functions using vertical NAND flash memory [PDF]
Nature CommunicationsPhysical Unclonable Functions (PUFs) can address the demand for enhanced hardware security. Vertical NAND (V-NAND) flash memory is the most commercialized non-volatile memory.
Sung-Ho Park +5 more
doaj +2 more sources