Results 31 to 40 of about 445 (155)
MicromachinesThe program disturbance characteristics of three-dimensional (3D) vertical NAND flash cell array architecture pose a critical reliability challenge due to the lower unselected word line (WL) pass bias (Vpass) window. In other words, the key contradiction
Kaikai You +3 more
doaj +1 more source
Advanced Functional Materials, Volume 36, Issue 23, 19 March 2026.This study establishes a materials‐driven framework for entropy generation within standard CMOS technology. By electrically rebalancing gate‐oxide traps and Si‐channel defects in foundry‐fabricated FDSOI transistors, the work realizes in‐materia control of temporal correlation – achieving task adaptive entropy optimization for reinforcement learning ...
Been Kwak +14 more
wiley +1 more source
GIDL 스트레스 조건 하에서 나노 크기 PMOSFET 열화 분석 [PDF]
, 2017 학위논문 (석사)-- 서울대학교 대학원 공과대학 전기·정보공학부, 2017. 8. 이종호.The device degradation under gate-induced drain leakage (GIDL) mode stress is studied in nano-scale p-MOSFET for DRAM peripheral circuit.
조수앙
core
Advanced Materials, Volume 37, Issue 50, December 17, 2025.HfO2‐based ferroelectric materials are promising for next‐generation memory technologies by providing outstanding performance aligning with data‐centric computing needs. This review details recent advancements in materials, devices, and integration for HfO2‐based memories, with the goal of identifying both the technological opportunities and remaining ...
Zuopu Zhou +9 more
wiley +1 more source
, 2018 학위논문 (박사)-- 서울대학교 대학원 : 공과대학 전기·컴퓨터공학부, 2018. 8. 박병국, 박영준.We report a method and experiment to detect the transport of the lattice phonons generated by hot electrons during the MOSFET operation.
유낙원
core
MicromachinesTo address the severe gate-induced drain leakage (GIDL) issue in fully depleted germanium-on-insulator (FD-GeOI) multi-subchannel tunneling field-effect transistors (MS TFETs), this paper proposes a stepped gate oxide (SGO) structure.
Rui Chen +6 more
doaj +1 more source
Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study
IEEE Access, 2020 The leakage mechanisms of inefficient volume depletion and lateral band to band tunneling (L-BTBT) restrict the scaling of SOI-junctionless (JL) FETs. Therefore, in this article, we investigate the scalability of the SOI-JLFETs by incorporating a ground ...
Aakash Kumar Jain +1 more
doaj +1 more source
1 Transistor‐Dynamic Random Access Memory as Synaptic Element for Online Learning
Advanced Intelligent Systems, Volume 7, Issue 8, August 2025.This work demonstrates the feasibility of utilizing capacitor‐less 1 transistor(1 T)‐dynamic random access memory as synaptic element with multilevel capability, large dynamic range of conductance, high linearity, ultralow energy consumption, high endurance exceeding 1015 cycles, and large integration density for artificial‐intelligence‐of‐things edge ...
MD Yasir Bashir +2 more
wiley +1 more source
MicromachinesThrough detailed experimental and modeling activities, this paper investigates the origin of the temperature dependence of the Erase operation in 3D nand flash arrays.
David G. Refaldi +4 more
doaj +1 more source
Stacked Nanosheet Gate‐All‐Around Morphotropic Phase Boundary Field‐Effect Transistors
Advanced Science, Volume 12, Issue 18, May 15, 2025.This study proposes a material design using ferroelectric‐antiferroelectric mixed‐phase HZO to achieve steep subthreshold swing and non‐hysteretic on‐current enhancement in morphotropic phase boundary field‐effect transistors (MPB‐FETs). For the first time, two‐stacked nanosheet GAA MPB‐FETs with optimized HZO are demonstrated, validating superior ...
Sihyun Kim +3 more
wiley +1 more source