Results 41 to 50 of about 445 (155)
Trap-assisted 터널링 GIDL 전류에서 RTN을 발생시키는 절연체 또는 실리콘 내부 트랩 사이트 특성과 트랩핑 메커니즘 분석 [PDF]
, 2016 학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 2. 신형철.Variable retention time (VRT) phenomenon is one of the main sources which degrade the retention time of DRAM cell, and this phenomenon becomes recently serious issue in DRAM cell transistor. Through various
유성원
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Alpenverein : Die Städter entdecken die Alpen [PDF]
, 2007 The Deutsche und Österreichische Alpenverein resulted from a merger of the Österreichischer Alpenverein founded in 1862 with the Deutsche Alpenverein in 1873.
Gidl, Anneliese, Anneliese Gidl
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Enhancing Device Performance with High Electron Mobility GeSn Materials
Advanced Electronic Materials, Volume 11, Issue 5, April 2025.Vertical gate‐all‐around nanowire n‐FETs based on GeSn‐alloys with Sn‐contents of 8% and 11% are presented. A great improvement in Ion, gm, and SS is found with increased Sn‐content. A fivefold increase in on‐current is observed for 11%‐GeSn compared to Ge, underlining the potential of GeSn for nanoelectronics applications.
Yannik Junk +10 more
wiley +1 more source
Role of mechanical stress on the electrothermal and OFF state current in scaled FinFET devices
Scientific ReportsThe electrothermal characteristics and leakage current of a tall FinFET device were investigated using the hydrodynamic transport model coupled with a quantum-corrected diffusive transport mechanism-based TCAD simulation.
Shubham, Rajan Kumar Pandey
doaj +1 more source
Dual-Doped Cylindrical Bit-Line Pad for High-Efficiency Bulk Erase in V-NAND Flash
IEEE AccessWe propose a novel dual-doped cylindrical bit-line (DDC-BL) pad structure for vertical NAND (V-NAND) flash memory to enable efficient bulk erase operation through direct hole injection.
Choasub Kim +4 more
doaj +1 more source
A new GIDL erase compact model of 3D NAND flash memory with proper capture cross section
, 2022 학위논문(석사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022.2. 신형철.3차원 수직 channel 낸드 플래시 메모리는 bit density를 향상시키는 방향으로 진화되어왔다. 최근에는 3차원 낸드 플래시 메모리의 bit density를 더욱 향상시키기 위해 CMOS under array 구조가 사용된다.
이걸
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n-Channel bulk and DTMOS FinFETs: Investigation of GIDL and gate leakage currents
, 2016 In this work GIDL (Gate Induced Drain Leakage) and Gate Leakage Currents (Ig) have been experimentally investigated for different dimensions of Bulk FinFETs with and without Dynamic Threshold MOS configuration (DTMOS) in linear and saturation regions ...
Caio Malingre Magan +9 more
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SiGe-Surrounded Bitline Structure for Enhancing 3D NAND Flash Erase Speed
Applied SciencesThree-dimensional NAND Flash has adopted the cell-over-peripheral (COP) structure to increase storage density. Unlike the conventional structure, the COP structure cannot directly increase the channel potential via substrate bias during the erase ...
Dohyun Kim, Wonbo Shim
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European Journal of Cancer Care, Volume 2025, Issue 1, 2025.Background: To systematically review the risk factors for central venous access device (CVAD)–associated complications in pediatric patients with cancer. Methods: A scoping review with systematic search criteria was conducted using PubMed, Embase, and CINAHL databases from 2012 to 2022. Cohort studies and the control arm of randomized controlled trials,
Jenna L. Nunn +6 more
wiley +1 more source
Correlation between hot-carrier-induced interface states and GIDL current increase in N-MOSFET's [PDF]
, 1998 Correlation between created interface states and GIDL current increase in n-MOSFET's during hot-carrier stress is quantitatively discussed. A trap-assisted two-step tunneling model is used to relate the increased interface-state density (ADH) with the ...
Lo, HB +4 more
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